Gilson I. Wirth

Atomistic approach to variability of bias-temperature instability in circuit simulations

A blueprint for an atomistic approach to introducing time-dependent variability into a circuit simulator in a realistic manner is demonstrated. The approach is based on previously proven physics of stochastic properties of individual gate oxide defects and their impact on FET operation. The proposed framework is capable of following defects with widely distributed time scales (from fast to quasi-permanent), thus seamlessly integrating random telegraph noise (RTN) effects with bias temperature instability (BTI). The use of industry-standard circuit simulation tools allows for studying realistic workloads and the interplay of degradation of multiple FETs.

Response of a single trap to AC negative Bias Temperature stress

We study the properties of a single gate oxide trap subjected to AC Bias Temperature Instability (BTI) stress conditions by means of Time Dependent Defect Spectroscopy. A theory for predicting the occupancy of a single trap after AC stress is developed based on first order kinetics and verified on experimental data. The developed theory can be used to develop circuit simulators and predict time dependent variability.

Compact Modeling of Statistical BTI Under Trapping/Detrapping

The aging process due to negative bias temperature instability (NBTI) is a key limiting factor of circuit lifetimes in CMOS design. Recent NBTI data exhibits an excessive amount of randomness and fast recovery, which are difficult to be handled by conventional power-law model (tn). Such discrepancies further pose the challenge on long-term reliability prediction under statistical variations and dynamic voltage scaling (DVS) in real circuit operation. To overcome these barriers, this paper: 1) practically explains the aging statistics due to randomness in number of traps with the log(t) model, accurately predicting the mean and variance shift; 2) proposes cycle-to-cycle model (from the first principles of trapping) to handle aging under multiple supply voltages, predicting the nonmonotonic behavior under DVS; 3) presents a long-term model to estimate a tight upper bound of dynamic aging over multiple cycles; and 4) comprehensively validates the new set of aging models with 65-nm statistical silicon data. Compared with previous models, the new set of aging models capture the aging variability and the essential role of the recovery phase under DVS, reducing unnecessary guard banding during the design stage.

Logarithmic behavior of the degradation dynamics of metal–oxide–semiconductor devices

In this paper the authors describe a simple theoretical statistical model of the process of relaxation in metal–oxide–semiconductor devices that governs the degradation. Basically, starting from an initial state where a given number of traps are occupied, the dynamics of the relaxation process is measured, and the density of occupied traps and its fluctuations (second moment) as a function of time are calculated. Our theoretical results show an emergent logarithmic behavior for the density of occupied traps: , i.e., the degradation is logarithmic and its amplitude depends only on the temperature and the Fermi level (applied bias voltage) of the device.

Using built-in sensors to cope with long duration transient faults in future technologies

Transients spanning more than one clock cycle will challenge soft error tolerant designs for future technologies. To face this problem, a low overhead technique that uses bulk built-in current sensors and recomputation is proposed here.

Statistical model for MOSFET low-frequency noise under cyclo-stationary conditions

A statistical model for the low-frequency (LF) noise behavior of MOSFETs under cyclo-stationary excitation is presented. The model is based on discrete device physics quantities, which are shown to cause statistical variability in LF noise behavior. Good agreement between experimental data, Monte Carlo simulations and model is demonstrated.

Simulation Evaluation of an Implemented Set of Complementary Bulk Built-In Current Sensors With Dynamic Storage Cell

This paper describes the design, the physical implementation, and the test procedure for a complementary pair of bulk built-in current sensors (Bulk-BICS) circuits, intended to detect single-event transients (SETs) induced by ionizing radiation on n- and p-type metal-oxide-semiconductor transistors. Electrical characterization of the prototype chip was performed, and the results are presented here. While not subjected to actual ionizing radiation, the performance of the manufactured integrated circuit is evaluated from its response to electrical test signals.

Modeling the sensitivity of CMOS circuits to radiation induced single event transients

An accurate and computer efficient analytical model for the evaluation of integrated circuit sensitivity to radiation induced single event transients is presented. The key idea of the work is to exploit a model that allows the rapid determination of the sensitivity of any MOS circuit to single event transients (SETs), without the need to run circuit level simulations. To accomplish this task, both single event transient generation and its propagation through circuit logic stages are characterized and modeled. The model predicts whether or not a particle hit generates a transient pulse which may propagate to the next logic gate or memory element. The electrical masking (attenuation) of the transient pulse as it propagates through each stage of logic until it reaches a memory element is also modeled. Model derivation is in strong relation with circuit electrical behavior, being consistent with technology scaling. The model is suitable for integration into CAD-Tools, intending to make automated evaluation of circuit sensitivity to SEU possible.

Circuit Design for Reliability

This book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units. The authors provide readers with techniques for state of the art and future technologies, ranging from technology modeling, fault detection and analysis, circuit hardening, and reliability management.

Statistical RTS model for digital circuits.

Abstract In this work we study the variation in drain current of MOS transistors due to the capture and emission of electrons at interface states (traps), called random telegraph signal (RTS). Usually, RTS is studied in frequency domain. However, for digital circuits, it is more appropriate to use time-domain representations. The time-domain representation here proposed models the effect of RTS on I ds as instantaneous Vt shifts. We introduce a statistical numerical approach for computing the total Δ Vt of the transistor considering all the traps in the interface. The method analyses the effect of non-uniform charge densities along the channel. To show the applicability of the methodology to circuit analysis on the electrical level, the model is applied to characterize read and write instability failures caused by RTS on a 6T-SRAM cell.