Gustavo Neuberger

Designing fault-tolerant techniques for SRAM-based FPGAs

FPGAs have become prevalent in critical applications in which transient faults can seriously affect the circuits operation. We present a fault tolerance technique for transient and permanent faults in SRAM-based FPGAs. This technique combines duplication with comparison (DWC) and concurrent error detection (CEO) to provide a highly reliable circuit while maintaining hardware, pin, and power overheads far lower than with classic triple-modular-redundancy techniques.

A multiple bit upset tolerant SRAM memory

SRAMs are used nowadays in almost every electronic product. However, as technology shrinks transistor sizes, single and multiple bit upsets only observable in space applications previously are now reported at ground level. This article presents a high level technique to protect SRAM memories against multiple upsets based on correcting codes. The proposed technique combines Reed Solomon code and Hamming code to assure reliability in presence of multiple bit flips with reduced area and performance penalties. Multiple upsets were randomly injected in various combinations of memory cells to evaluate the robustness of the method. The experiment was emulated in a Virtex FPGA platform. Results show that 100% of the injected double faults and a large amount of multiple faults were corrected by the method.

Designing and testing fault-tolerant techniques for SRAM-based FPGAs

This paper discusses fault-tolerant techniques for SRAM-based FPGAs. These techniques can be based on circuit level modifications, with obvious modifications in the programmable architecture, or they can be implemented at the high-level description, without modification in the FPGA architecture. The high-level method presented in this work is based on Triple Modular Redundancy (TMR) and a combination of Duplication Modular Redundancy (DMR) with Concurrent Error Detection (CED) techniques, which are able to cope with upsets in the combinational and in the sequential logic. The methodology was validated by fault injection experiments in an emulation board. Results have been analyzed in terms of reliability, input and output pin count, area and power dissipation.

Protecting Chips Against Hold Time Violations Due to Variability

With the development of Very-Deep Sub-Micron technologies, process variability is becoming increasingly important and is a very important issue in the design of complex circuits. Process variability is the statistical variation of process parameters, meaning that these parameters do not have always the same value, but become a random variable, with a given mean value and standard deviation. This effect can lead to several issues in digital circuit design. The logical consequence of this parameter variation is that circuit characteristics, as delay and power, also become random variables. Because of the delay variability, not all circuits will now have the same performance, but some will be faster and some slower. However, the slowest circuits may be so slow that they will not be appropriate for sale. On the other hand, the fastest circuits that could be sold for a higher price can be very leaky, and also not very appropriate for sale. A main consequence of power variability is that the power consumption of some circuits will be different than expected, reducing reliability, average life expectancy and warranty of products. Sometimes the circuits will not work at all, due to reasons associated with process variations. At the end, these effects result in lower yield and lower profitability. To understand these effects, it is necessary to study the consequences of variability in several aspects of circuit design, like logic gates, storage elements, clock distribution, and any other that can be affected by process variations. The main focus of this book will be storage elements.

Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies

Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub- 100nm technologies. In this work we investigate the variability of flip flop race immunity in 130nm and 90nm low power CMOS technologies. An on-chip measurement technique with resolution of ˜1ps is used to characterize hold time violations of flip flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Statistical die-to die variations of hold time violations are measured various register-to-register configurations and show overall 3σ die-to-die standard deviations of 12–16% Mathematical methods to separate the measured variability between systematic and random variability are discussed, and the results presented. They show that while systematic variability is the major issue in 130nm, it is significantly decreased in 90nm technology due to better process control. Another important point is that the race immunity decreases about 30% in 90nm, showing that smaller clock skews can lead to violations in 90nm.

Protecting digital circuits against hold time violation due to process variability

Statistical process variations are a critical issue to define circuit design strategies to ensure high yield in sub-100nm technologies. This work focuses on hold time violation probabilities in sub-100 nm technologies. The variability in flip-flop race immunity and clock skew is evaluated, and a methodology for the estimation of hold time violation probability is developed. This violation probability is analyzed at different technologies, flip-flop strength, supply voltage and padding. Then three different methods to protect against hold time violations are evaluated: Vdd reduction, race immunity increase, and padding. Each of them has different advantages and drawbacks that must be taken into account. It is shown that at design time the most effective method is padding. An algorithm to automatically insert padding in digital circuits considering process variability is presented. The proposed algorithm will be evaluated compared to other ways to protect against violations.

Statistical Characterization of Hold Time Violations in 130nm CMOS Technology

Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub-100nm technologies. In this work we present an on-chip measurement technique to characterize hold time violations of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Using a precise programmable clock-to-data skew generation circuit, a measurement resolution of ~1 ps is achieved to emulate race conditions. Statistical variations of hold time violations are measured in a 130nm low-power CMOS technology for various register-to-register configurations and show 3sigma die-to-die standard deviations of up to 15%

Systematic and Random Variability

The total variability observed in the measured data may come from different sources. They may be wafer-to-wafer, die-to-die, intra-die, and may come from systematic or random sources.

Circuits Under Test

The circuits can be very sensitive to process variability, but different circuits can have different sensibilities. To have representative results, the circuits that will be fabricated to be tested must be carefully chosen. First, the sensitivity of the logic circuits will be verified through simulation in 130 and 90 nm technologies, however only the results for 90 nm will be shown in this chapter. Using MC simulations, the sensitivity of inverters (representing generic combinational circuits) and FFs will be measured. Combining them, we will verify if hold time violations are a potential problem, and if they can be generated by process variations. Finally, the circuits chosen for fabrication and measurement in silicon will be shown.

Protecting Circuits Against Hold Time Violations

In this chapter, we show how to protect digital circuits against hold time violations due to process variability. First, a motivation in this issue is drawn. Then different options of how to provide the protection are presented.