Lucas Compassi Severo

Automatic Synthesis of Analog Integrated Circuits Including Efficient Yield Optimization

In this chapter, the authors show the main aspects and implications of automatic sizing, including yield. Different strategies for accelerating performance estimation and design space search are addressed. The analog sizing problem is converted into a nonlinear optimization problem, and the design space is explored using metaheuristics based on genetic algorithms. Circuit performance is estimated by electrical simulations, and the generated optimal solution includes yield prediction as a design constraint. The method was applied for the automatic design of a 12-free-variables two-stage amplifier. The resulting sized circuit presented 100 % yield within a 99 % confidence interval, while achieving all the performance specifications in a reasonable processing time. The authors implemented an efficient yield-oriented sizing tool which generates robust solutions, thus increasing the number of first-time-right analog integrated circuit designs.

Simulated Annealing to Improve Analog Integrated Circuit Design: Trade-Offs and Implementation Issues

The design of analog integrated circuits is complex because it involves several aspects of device modeling, computational methodologies, and human experience. Nowadays, the well-stablished CMOS (Complementary Metal-Oxide-Semiconductor) technology is mandatory in most of the integrated circuits. The basic devices are MOS transistors, whose manufacturing process is well understood and constantly updated in the design of small devices. Detailed knowledge of the devices technology is needed for modeling all aspects of analog design, since there is a strong dependency between the circuit behavior and the manufacturing process.

SAMPA Chip: The New 32 Channels ASIC for the ALICE TPC and MCH Upgrades

This paper presents the test results of the second prototype of SAMPA, the ASIC designed for the upgrade of read-out front end electronics of the ALICE Time Projection Chamber (TPC) and Muon Chamber (MCH). SAMPA is made in a 130 nm CMOS technology with 1.25 V nominal voltage supply and provides 32 channels, with selectable input polarity, and three possible combinations of shaping time and sensitivity. Each channel consists of a Charge Sensitive Amplifier, a semi-Gaussian shaper and a 10-bit ADC; a Digital Signal Processor provides digital filtering and compression capability. In the second prototype run both full chip and single test blocks were fabricated, allowing block characterization and full system behaviour studies. Experimental results are here presented showing agreement with requirements for both the blocks and the full chip.

Testing fully differential amplifiers using common mode feedback circuit: A case study

This paper presents a simple and low-cost test methodology applied to fully differential amplifiers (FDAs). This kind of amplifier needs a common mode feedback (CMFB) circuit to keep the output common mode tightly controlled. In this work we propose the reuse of the CMFB circuit of FDAs as an embedded checker to ease the test of the whole amplifier, increasing the observability of faults occurring either in the amplifier or in the CMFB block. Catastrophic faults are injected into these two circuits by means of SPICE simulations, considering a 0.18μm FDA as case study. Transient and DC (Direct Current) tests are performed and the fault coverage is evaluated. Simulation results point to high fault coverage, while only the common mode feedback signal needs to be monitored. This way, a low-cost and low area overhead test methodology is achieved with affordable test time.

A methodology for the automatic design of operational amplifiers including yield optimization

This paper presents an automatic sizing methodology for CMOS operational amplifiers considering process parameter variations in submicron technologies. These circuits are very sensitive to process variations, which cause mismatch. The proposed methodology comprises simultaneous optimization of power dissipation, gate area and yield prediction, exploring effectively the design space in all transistor operation regions. Yield is estimated by Monte Carlo analysis, which is performed only for the best solutions candidates in the optimization procedure. A Miller OTA and a folded cascode amplifier are designed in 0.18μm technology using the proposed methodology. Results show the increase in the circuit yield comparing to the same design without yield prediction, while keeping the power and area budget and a reasonable computational time.

Current mode 1.2-Gbps SLVS transceiver for readout front-end ASIC

This work presents the design and experimental results of a current mode Scalable Low-Voltage Signaling (SLVS) transceiver in 130 nm CMOS technology. The proposed transmitter includes a feedback control which reduces the common-mode voltage variations in terms of the Vds voltage of the bias transistor, and an enable/disable operation mode, which minimizes the power consumption when data transmission is not requested. A rail-to-rail comparator topology was used to design the receiver circuit being robust to transient common-mode variations with low power consumption and high speed. The experimental DC power consumption of the transceiver is 4.6 mW at 1.25V power supply, where 1.1 mW is consumed by the receiver and 3.5 mW by the transmitter. The eye diagram proves the proper dynamic operation of the circuit until a data rate of 1.2Gbps.

A digitally tunable 4th-order Gm-C low-pass filter for multi-standards receivers

This paper presents a digitally tunable 4th-order Gm-C low-pass filter (LPF) for multi-standards radio receivers. The cutoff frequency tuning is provided by changing the transconductance of a reconfigurable operational transconductance amplifier (OTA). Two control bits are employed to digitally control the OTA transconductance and also the power consumption. This LPF is designed in a 180 nm CMOS process and powered by a 1.8 V power supply. Post-layout simulation analysis indicate that this flexibility provides a cutoff frequency of 2.54/5.11/7.68/10.29 MHz with a power consumption ranging from 10.27 to 12.69 mW. The designed filter achieves an IIP3 of 4.14 dbm for a signal bandwidth of 10.29 MHz and electrical characteristics comparable to recent published works in the literature.