Arthur Campos de Oliveira

0.3 V supply, 17 ppm/°C 3-transistor picowatt voltage reference

In this work a novel resistorless MOSFET 3-transistor voltage reference that operates in the picowatt range and occupies very small area is proposed. The circuit is based on a self-cascode structure that is biased in subthreshold condition using the leakage current provided by a reverse biased MOSFET diode. Its electrical behavior is analytically described and a design methodology is presented to allow the transistors sizing for optimal temperature compensation. Simulation results for a standard 130 nm CMOS process are presented to validated the proposed circuit topology. A reference voltage of 85 mV is obtained with a temperature coefficient (TC) of 17.4 ppm/°C and consuming only 7 pW under 0.3 V of power supply at room temperature. Monte Carlo analysis shows that the reference voltage σ/μ<; 3.3% and that 90% of the samples present TC<;50 ppm/°C without trimming.

A 0.3 V, high-PSRR, picowatt NMOS-only voltage reference using zero- V T active loads

A low-voltage high-PSRR CMOS voltage reference operating with picowatt power consumption is presented. The voltage reference is generated from the threshold voltage (VT) difference of two transistors biased in weak inversion. The VT difference is achieved through its dependence with the transistor dimensions. The high-PSRR is obtained using zero-VT transistors as active loads. The final circuit was designed in a 130 nm CMOS process and occupies around 0.0007 mm2 of silicon area while consuming just 18.5 pW at 27°C. Post-layout simulations present a 62 mV reference voltage with a temperature coefficient of 15 ppm/°C, for a temperature range from -25 to 125 °C and a Power Supply Rejection Ratio (PSRR) of -68.7 dB at 0.3 V of supply voltage.

A 0.45 V, 93 pW temperature-compensated CMOS voltage reference

This paper presents a self-biased self-cascode MOSFET (SBSCM) voltage reference that can operate with supply voltages as low as 0.45 V while consuming tens of pW. The voltage reference is generated through the self-cascode MOSFET (SCM) using transistors with different threshold voltages and is implemented in a way that the SCM itself composes the bias circuitry. The proposed topology was implemented in a standard 0.18 μm CMOS process and post-layout simulation results in a reference voltage of 248 mV with temperature coefficient around 7 ppm/oC for the 0 oC to 125 oC range, while consuming 93 pW at room temperature with 0.45 V of supply voltage. The occupied silicon area is 0.002 mm2.

Picowatt, 0.45–0.6 V Self-Biased Subthreshold CMOS Voltage Reference

In this paper, a self-biased temperature-compensated CMOS voltage reference operating at picowatt-level power consumption is presented. The core of the proposed circuit is the self-cascode MOSFET (SCM) and two variants are explored: a self-biased SCM (SBSCM) and a self-biased NMOS (SBNMOS) voltage reference. Power consumption and silicon area are remarkably reduced by combining subthreshold operation with a self-biased scheme. Trimming techniques for both circuits are discussed aiming at the reduction of the process variations impact. The proposed circuits were fabricated in a standard 0.18-

Testing fully differential amplifiers using common mode feedback circuit: A case study

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A sub-1 V, nanopower, ZTC based zero-VT temperature-compensated current reference

CMOS process. Measurement results from 24 samples of the same batch show that both circuits herein proposed can operate at 0.45/0.6 V minimum supply voltage, consuming merely 55/184 pW at room temperature. Temperature coefficient (TC) around 104/495 ppm/°C across a temperature range from 0 to 120 °C was measured. Employment of a trimming scheme allows a reduction of the average TC to 72.4/11.6 ppm/°C for the same temperature range. Both variants of the proposed circuit achieve a line sensitivity of 0.15/0.11 %/V and a power supply rejection better than −44/−45 dB from 10 to 10 kHz. In addition, SBSCM and SBNMOS prototypes occupy a silicon area of 0.002 and 0.0017 mm2, respectively.

An ultra-low power high-order temperature- compensated CMOS voltage reference

This paper presents a simple and low-cost test methodology applied to fully differential amplifiers (FDAs). This kind of amplifier needs a common mode feedback (CMFB) circuit to keep the output common mode tightly controlled. In this work we propose the reuse of the CMFB circuit of FDAs as an embedded checker to ease the test of the whole amplifier, increasing the observability of faults occurring either in the amplifier or in the CMFB block. Catastrophic faults are injected into these two circuits by means of SPICE simulations, considering a 0.18μm FDA as case study. Transient and DC (Direct Current) tests are performed and the fault coverage is evaluated. Simulation results point to high fault coverage, while only the common mode feedback signal needs to be monitored. This way, a low-cost and low area overhead test methodology is achieved with affordable test time.

A 0.12–0.4 V, Versatile 3-Transistor CMOS Voltage Reference for Ultra-Low Power Systems

A nano-ampere current reference with temperature compensation operating is presented. The reference current is generated biasing a zero-VT transistor near its Zero-temperature coefficient (ZTC) point. Two versions were implemented in a 180 nm CMOS process. Both are designed using the same thermal compensation principle, but the second version uses an auxiliary circuit to compensate process variation. The circuits occupy 0.01 and 0.018 mm2 of silicon area while consuming around 30.5 and 122 nW at 27° C, respectively. Post-layout simulations present a reference current of 10.86 and 10.95 nA with a average temperature coefficient of 108 and 127 ppm/°C (100 Samples), under a temperature range from −20 to 120 °C, and a line sensitivity of 0.54 and 0.86 %/V at 0.9 V to 1.8 V of supply voltage, respectively.

An optimization-based methodology for efficient design of fully differential amplifiers

This work presents an ultra-low power low-voltage high-order temperature-compensated voltage reference. The proposed circuit is based on the self-cascode MOSFET (SCM) and explores the dependence of the threshold voltage (VT) with the transistor dimensions. The SCM is biased by the leakage current of a zero-VT transistor for PSRR improvement. The proposed circuit is composed only of 3 transistors. The high-order temperature compensation is achieved through a bulk-driven scheme. Additionally, the proposed high-order compensation also attenuates the mismatch variability of the voltage reference. Post-layout simulation results for a standard 130 nm CMOS process are presented. A voltage reference of 90.5 mV with a 1 ppm/°C temperature coefficient (TC) is achieved at typical corner. The circuit can operate at a minimum supply voltage as low as 0.3 V while consuming 43.7 pW at room temperature.