Paola Galbiati

BCD8 from 7V to 70V: a new 0.l8μm Technology Platform to Address the Evolution of Applications towards Smart Power ICs with High Logic Contents

This paper presents the 8th BCD generation integrating power and high voltage devices in a 0.18 μm technology node platform. Both dense 1.8 V and 3.3 V logic CMOS are available to realize complex monolithic solutions in the field of smart power applications.

Smart power approaches VLSI complexity

This paper reviews the latest trends in the mixed power process field driven by the need to integrate increasing numbers of functions on the same chip. The more recent BCD (bipolar-CMOS-DMOS) examples are a demonstration of how smart power technology evolves following, with some delay, the road maps of VLSI CMOS and BiCMOS. The issues behind the trend to converge to a common technology platform, maintaining the peculiar aspects of power functions integration, are discussed, as well as new possible realizations in the field of super smart power ICs.

Via first approach optimisation for Through Silicon Via applications

Through Silicon Via (TSV) is a very attractive solution for 3D stacking. Currently the main technique in industrial TSV processes is the via-last approach. But the via-first approach has also many advantages and in particular allows the use of high thermal budget materials for high voltage applications.

LDMOS implementation by large tilt implant in 0.6 /spl mu/m BCD5 process, flash memory compatible

This paper describes a method for integrating power LDMOS structures in a smart power Bipolar-CMOS-DMOS technology called BCD5 designed at 0.6 /spl mu/m, compatible with VLSI EPROM, EEPROM and flash non volatile memories (NVM). The compatibility between NVM and LDMOS is achieved replacing conventional DMOS manufacturing processes, consisting of high temperature diffusion steps, with an innovative approach that exploits large angle of tilt implantation technique.

Characteristics and applications of a 0.6 /spl mu/m bipolar-CMOS-DMOS technology combining VLSI non-volatile memories

This paper describes the 5th generation, designed at 0.6 /spl mu/m, of the BCD process family commercially introduced ten years ago. Called BCD5, this smart power process provides very dense and high performance bipolar, CMOS and DMOS functions and is compatible with VLSI EPROM, EEPROM and Flash Non-Volatile Memories. Extremely complex systems requiring analog, digital and power functions, /spl mu/P cores and significant amount of memories (hundreds of Kbits) can be realized in one chip (Super Smart Power integration) using BCD5.

A novel 0.16 μm — 300 V SOIBCD for ultrasound medical applications

The development of a new 0.16 μm SOIBCD technology integrating components with breakdown voltage higher than 300 V is here described. Process integration and mechanical stress due to buried oxide and lateral dielectric isolation was investigated with TCAD simulations, morphological analysis and Raman spectroscopy measurements. Component portfolio was derived from existing junction isolated (JI) 0.16 μm technologies and expanded with high voltage MOS. Stress induced by the full dielectric isolation is far from critical values. Breakdown voltages over 350 V were measured.

Design of a high side driver in multipower-BCD and VIPower technologies

Two junction isolated mixed processes named Multipower BCD (Bipolar-CMOS-DMOS) and VIPower (Vertical Intelligent Power) are discussed and compared in this paper. Their main difference regards the integration scheme of the DMOS power output, which has the drain contact placed respectively on the front or on the back of the die. The process flow-charts and the design rules are chosen to allow the integration of the same signal components. Two self protected power switches referred to positive supply (high side driver) have been fabricated in the two technologies and the pros and cons of the two approaches are discussed. 60V was the examined class of breakdown voltage, suitable for automotive applications.

190V N-channel lateral IGBT integration in SOI 0.35 µm BCD technology

The integration of 190 V N-Ch. ateral IGBT in SOI 0.35 mum shrunk BCD technology is described in this paper. LIGBT design optimization by simulation and silicon characterization data are here reported, highlighting the superior current capability of LIGBT with respect to equivalent power MOS. Behavior during high temperature reverse bias (HTRB) test was investigated and basic IGBT structure modified to minimize the stress induced effects. The novel device shows a very high saturation current (around 2.5 kA cm-2) and excellent electrical parameter stability after HTRB stress test.