Hung-Manh Pham

Low-overhead fault-tolerance technique for a dynamically reconfigurable softcore processor

In this paper, we propose a new approach to implement a reliable softcore processor on SRAM-based FPGAs, which can mitigate radiation-induced temporary faults (single-event upsets (SEUs)) at moderate cost. A new Enhanced Lockstep scheme built using a pair of MicroBlaze cores is proposed and implemented on Xilinx Virtex-5 FPGA. Unlike the basic lockstep scheme, ours allows to detect and eliminate its internal temporary configuration upsets without interrupting normal functioning. Faults are detected and eliminated using a Configuration Engine built on the basis of the PicoBlaze core which, to avoid a single point of failure, is implemented as fault-tolerant using triple modular redundancy (TMR). A softcore processor can recover from configuration upsets through partial reconfiguration combined with roll-forward recovery. SEUs affecting logic which are significantly less likely than those affecting configuration are handled by checkpointing and rollback. Finally, to handle permanent faults, the tiling technique is also proposed. The new Enhanced Lockstep scheme requires significantly shorter error recovery time compared to conventional lockstep scheme and uses significantly smaller number of slices compared to known TMR-based design (although at the cost of longer error recovery time). The efficiency of the proposed approach was validated through fault injection experiments.

UPaRC—Ultra-fast power-aware reconfiguration controller

Dynamically reconfigurable architectures, which can offer high performance, are increasingly used in different domains. High-speed reconfiguration process can be carried out by operating at high frequency but can also augment the power consumption. Thus the effort on increasing performance by accelerating the reconfiguration should take into account power consumption constraints. In this paper, we present an ultra-fast power-aware reconfiguration controller (UPaRC) to boost the reconfiguration throughput up to 1.433 GB/s. UPaRC can not only enhance the system performance, but also auto-adapt to various performance and consumption conditions. This could enlarge the range of applications and optimize for each selected application during run-time. An investigation of reconfiguration bandwidths at different frequencies and with different bitstream sizes are experimentally quantified and presented. The power consumption measurements are also realized to emphasize energy-efficiency of UPaRC over state-of-the-art reconfiguration controllers-up to 45 times more efficient.

A Fault-Tolerant Layer for Dynamically Reconfigurable Multi-processor System-on-Chip

Parallel computing is an important trend of embedded system. One possible response to increasing requirements in computational power is to distribute tasks over various processors and let these processors operate in parallel. Soft-core processors and FPGAs require low Non-Recurring Engineering costs to develop such multi-processors systems. Furthermore, certain FPGAs allow dynamic partial run-time reconfiguration, but their high sensitivity to electronic defects can cause the system disfunction. This paper presents a fault-tolerant multi-processor system-on-chip based on the dynamic reconfiguration of the entire platform. Also, a modification of the standard methodology of the runtime self-reconfiguration, who facilitates the complex modular concept design, is presented in this paper.

Experiments of in-vehicle power line Communications

This book provides an insight on both the challenges and the technological solutions of several approaches, which allow connecting vehicles between each other and with the network. It underlines the trends on networking capabilities and their issues, further focusing on the MAC and Physical layer challenges. Ranging from the advances on radio access technologies to intelligent mechanisms deployed to enhance cooperative communications, cognitive radio and multiple antenna systems have been given particular highlight.

Evaluation of Fault-Mitigation Schemes for Fault-Tolerant Dynamic MPSoC

One trend dealing with the growing computational power needs is to implement multi-processor system-on-a-chip (MPSoC) using Commercial Off-The-Shelf (COTS) partially reconfigurable architectures. However the low Non-Recurring Engineering (NRE) cost solution provided by commercial FPGAs must take into account the high sensitivity to electronic defects. Fault-tolerance schemes, which prevent their architectures from being defective during products life-time, can decrease the system computing power. Therefore, building such fault-tolerant system needs an analytical model to analyze the effect of fault mitigation schemes on the system performance. This paper presents an analytical approach for a fault-tolerant dynamic multi-processor system-on-a-chip (FT-DyMPSoC) which is able to resist to predominant fault in FPGAs - Single Event Upset. The analytical model is introduced to assess the performance, the reliability and the trade-off of a fault-tolerant MPSoC system. Several comparisons with classical fault-tolerance solutions to enhance our solution advantages are also given.

Reconfigurable ECU communications in Autosar Environment

Reconfigurable architectures become popular in consumer applications as they require low Non-Recurring Engineering costs. Certain FPGA families provide the Dynamic Partial Reconfiguration (DPR) mechanism which allows to modify parts of a device on-the-fly. The high reliability constraints in automotive systems requires safe communications between ECUs (Electronic Control Unit). This paper presents a support for fault-tolerant communication modes among ECUs by the use of the dynamic reconfiguration paradigm. Also in this paper, a method of integrating dynamic reconfiguration in Autosar environment is presented.

Re 2 DA: Reliable and reconfigurable dynamic architecture

Exploiting partial reconfiguration of commercial FPGAs allows the construction of dynamic multi-processor system-on-chip (MPSoC). This solution offers many advantages such as: low development costs and maintains flexibility as well as high computation power. However, FPGAs are susceptible to electronic particles which can toggle configuration bit values and hence change the correct function of the design. Moreover, that could be important in critical applications which require safety and security. Hence using FPGA requires to integrate fault-tolerance schemes into the system. The reliable MPSoC system called Re2DA, presented in this paper, guarantee the system operation by the use of dynamic reconfiguration. Nearly no hardware overhead is required to perform fault-tolerant feature in the system while timing overhead is kept relatively low.