Luís Mendes

Automated design of radio-frequency single-ended switched capacitor arrays using genetic algorithms

This paper presents an automated synthesis procedure to design radio-frequency and microwave binary-weighted single-ended switched capacitor arrays (RFSSCAs) from user top-level specifications to components sizes. The method relies on closed-form symbolic mathematical expressions of the input impedance and quality factor of the RFSSCA. The genetic synthesis tool optimizes a fitness function based on user-specified performance constraints. The method determines several optimal solutions, which are completely independent of the starting point. Moreover, infeasible specifications are unambiguously detected. To validate the proposed design algorithm, two RFSSCAs are synthesized in a 0.35 mum CMOS technology and verified by the SpectreRF simulator of the Cadence design environment. The results show that the synthesis and simulation outcomes are in very good agreement.

Performance of Si-Integrated Wide-Band Single-Ended Switched Capacitor Arrays

A closed-form equation for the quality factor of CMOS or BiCMOS single-ended switched capacitor arrays (SSCAs), intended for radio-frequency (RF) and microwave switched tuning resonators, is presented and analyzed. This expression predicts accurately the SSCA quality factor (Qssca) with respect to the operation frequency and tuning control input. Important results arise from this equation, viz., Qssca shows a strong dependence on the reference cell electric parameters, presents a monotonically behavior with the tuning control input, is independent of the SSCA size (number of cells) and increases as the technology scales down. Besides that, new concepts are also introduced, namely, basic switch, reference switch, reference capacitor and reference cell. A 0.1 to 6 GHz SSCA, designed with standard 0.35 mum 2-poly 4-metal mixed-signal CMOS technology, is also described. The SSCA has a capacitive tuning range from 210 to 385 fF with a resolution capacitance of 25 fF. The theoretical results, obtained with the SSCA model, match the SSCA layout Spectrereg RF simulation.

A 130 nm CMOS LNA for 30 GHz applications

This paper presents the design of a 30 GHz low noise amplifier in a 130 nm CMOS technology. The amplifier is based on a cascode topology. The circuit uses autotransformers in the input and output matching networks. This design approach eliminates the necessity of the use of source degeneration and allows obtaining an ultra compact LNA. The amplifier presents a forward gain (S21) of 7.4 dB at 30 GHz with a bandwidth of 10 GHz, input and output VSWRs better than 1.22:1 and a noise figure of 3.7 dB. The LNA is unconditionally stable and consumes only 7 mW when supplied with 1.2 V. The amplifier fits an area of 0.08 mm2, which is one of the smallest areas reported.

Single-objective front optimization: application to rf circuit design

This paper proposes a new algorithm which promotes well distributed non-dominated fronts in the parameters space when a single-objective function is optimized. This lgorithm is based on µ-dominance concept and maxmin sorting scheme. Besides that, the paper also presents the results of the algorithm when it is used in the automated synthesis of optimum performance CMOS radio-frequency and microwave binary-weighted differential switched capacitor arrays (RFDSCAs). The genetic synthesis tool optimizes a fitness function which is based on the performance parameter of the RFDSCAs. To validate the proposed design methodology, a CMOS RFDSCA is synthesized, using a 0.25 ¼m BiCMOS technology.

A High-Performance Digitally Controlled LC Oscillator for Ku-Band Applications

A 13.5-15.5 GHz low phase noise digitally controlled LC VCO, designed in a 0.25 mum BiCMOS technology, is presented in this paper. The resonant circuit of the VCO uses a high performance radio-frequency differential binary-weighted switched capacitor array (RFDSCA) to cover the 2 GHz tuning band with a continuous tuning voltage of 5 V. The RFDSCA circuit was optimized using a new automated synthesis method in order to guarantee a VCO with minimum phase noise. The VCO presents a typical phase noise of -116 dB/Hz @ 1MHz and a maximum tuning sensitivity of 165 MHz/V. The VCO core works with a voltage supply of 3 V and has a current consumption of 5 mA. The results demonstrate the feasibility of implementing and using high performance RFDSCAs as digital tuning elements at operating frequencies up to tens of gigahertz.

Design Optimization of Radio Frequency Discrete Tuning Varactors

This work presents a procedure to automate the design of Si-integrated radio frequency (RF) discrete tuning varactors (RFDTVs). The synthesis method, which is based on evolutionary algorithms, searches for optimum performance RF switched capacitor array circuits that fulfill the design restrictions. The design algorithm uses the *** -dominance concept and the maximin sorting scheme to provide a set of different solutions (circuits) well distributed along an optimal front in the parameter space (circuit size and component values). Since all the solutions present the same performance, the designer can select the circuit that is best suited to be implemented in a particular integration technology. To assess the performance of the synthesis procedure, several RFDTV circuits, provided by the algorithm, were designed and simulated using a

Design of Radio-Frequency Integrated CMOS Discrete Tuning Varactors Using the Particle Swarm Optimization Algorithm

0.18\mu\textrm{m}

A low power low phase noise wide switched tuned band LC VCO for S band applications

CMOS technology and the Cadence Virtuoso Design Platform. The comparisons between the algorithm and circuit simulation results show that they are very close, pointing out that the proposed design procedure is a powerful design tool.

A 5GHz/1.8V CMOS active balun integrated with LNA

This paper presents an automated design procedure of radio- frequency integrated CMOS discrete tuning varactors (RFDTVs). This new method use the maximin and the particle swarm optimization (PSO) algorithms to promote well distributed non-dominated fronts in the parameters space when a single-objective function is optimized. The fitness function used in the search tool is proportional to the RFDTV quality factor. The outcome of the automated design method comprises a set of RFDTV circuits, all having the same maximum performance. Each solution, which corresponds to one RFDTV circuit, is defined by the number of cells and by the circuit components values. This approach allows the designer to choose among several possible circuits the one that is easier to implement in a given CMOS process. To validate the effectiveness of the synthesis procedure proposed in this paper (PSO-method) comparisons with a design method based on genetic algorithms (GA-method) are presented. A 0.18 μ m CMOS radio-frequency binary-weighted differential switched capacitor array (RFDSCA) was designed and implemented (the RFDSCA is one of the possible topologies of the RFDTVs). The results show that both design methods are in very good agreement. However, the PSO technique outperforms the GA-method in the design procedure run time taken to accomplish the same performance results.

Substrate noise isolation improvement in a single-well standard CMOS process

This paper deals with the design problems associated to the implementation of low power wide tuning band low phase noise LC VCOs in low cost Si-integrated technologies. For that, a VCO was developed using a low cost 0.35 mum 2-poly 4-metal standard CMOS technology. The VCO uses a radio frequency switched varactor array (RFSVA) in the tank circuit in order to decrease the influence of the varactor tuning input on the oscillator phase noise. The VCO presents a continuous tuning band from 2.76 GHz to 3.36 GHz, a single-ended output power that ranges from -12 dBm to -6 dBm and a phase noise always lower than -117 dBc/Hz at an offset frequency of 1 MHz. Moreover, the two output ports of the VCO present return losses higher than 12.7 dB in the 600 MHz tuning band. The VCO core works with a voltage supply of 1.5 V and has a current consumption of 5 mA and the output buffers draws 18 mA from a 3 V voltage supply.