Maria João Rosário

Automated design of radio-frequency single-ended switched capacitor arrays using genetic algorithms

This paper presents an automated synthesis procedure to design radio-frequency and microwave binary-weighted single-ended switched capacitor arrays (RFSSCAs) from user top-level specifications to components sizes. The method relies on closed-form symbolic mathematical expressions of the input impedance and quality factor of the RFSSCA. The genetic synthesis tool optimizes a fitness function based on user-specified performance constraints. The method determines several optimal solutions, which are completely independent of the starting point. Moreover, infeasible specifications are unambiguously detected. To validate the proposed design algorithm, two RFSSCAs are synthesized in a 0.35 mum CMOS technology and verified by the SpectreRF simulator of the Cadence design environment. The results show that the synthesis and simulation outcomes are in very good agreement.

A Closed-Form Input Admittance Solution for RF and Microwave Switched Capacitor Arrays

The parallel equivalent circuit for radio-frequency and microwave single-ended switched capacitor arrays (SSCAs) is investigated. In particular, the SSCA equivalent capacitance and resistance are highlighted and predicted by new closed-form mathematic expressions. The behavior of the SSCA with the control input and frequency is also analyzed in detail. The proposed model shows that the SSCA admittance depends on frequency, integration technology parameters, circuit size and control input. An ultra-wide-band SSCA, designed with standard 0.35 mum 2P4M mixed-signal CMOS technology, is also presented and used to assess the model accuracy. The model predictions match the computer simulations.

A New On-Chip CMOS Active Balun Integrated With LNA

The design and simulation of an innovative monolithic active balun integrated with low noise amplifier, is described in this paper. The fully integrated circuit was implemented in a 0.35 mum AMS CMOS standard technology. The simulations, optimized to noise performance, minimum differential phase and magnitude error, were performed with BSIM3 model Circuit simulations present 20.6dB differential power gain at 2.4 GHz, a phase and a transducer gain magnitude errors less than 0.2deg and 0.04 dB, respectively, in a 1GHz span around 2.4 GHz, a 3.7dB noise figure, a 2 dBm output-referred ldB compression point, 50 Omega input and output match, while drawing 11mA from a 3V power supply.

Performance of Si-Integrated Wide-Band Single-Ended Switched Capacitor Arrays

A closed-form equation for the quality factor of CMOS or BiCMOS single-ended switched capacitor arrays (SSCAs), intended for radio-frequency (RF) and microwave switched tuning resonators, is presented and analyzed. This expression predicts accurately the SSCA quality factor (Qssca) with respect to the operation frequency and tuning control input. Important results arise from this equation, viz., Qssca shows a strong dependence on the reference cell electric parameters, presents a monotonically behavior with the tuning control input, is independent of the SSCA size (number of cells) and increases as the technology scales down. Besides that, new concepts are also introduced, namely, basic switch, reference switch, reference capacitor and reference cell. A 0.1 to 6 GHz SSCA, designed with standard 0.35 mum 2-poly 4-metal mixed-signal CMOS technology, is also described. The SSCA has a capacitive tuning range from 210 to 385 fF with a resolution capacitance of 25 fF. The theoretical results, obtained with the SSCA model, match the SSCA layout Spectrereg RF simulation.

A 130 nm CMOS LNA for 30 GHz applications

This paper presents the design of a 30 GHz low noise amplifier in a 130 nm CMOS technology. The amplifier is based on a cascode topology. The circuit uses autotransformers in the input and output matching networks. This design approach eliminates the necessity of the use of source degeneration and allows obtaining an ultra compact LNA. The amplifier presents a forward gain (S21) of 7.4 dB at 30 GHz with a bandwidth of 10 GHz, input and output VSWRs better than 1.22:1 and a noise figure of 3.7 dB. The LNA is unconditionally stable and consumes only 7 mW when supplied with 1.2 V. The amplifier fits an area of 0.08 mm2, which is one of the smallest areas reported.

Single-objective front optimization: application to rf circuit design

This paper proposes a new algorithm which promotes well distributed non-dominated fronts in the parameters space when a single-objective function is optimized. This lgorithm is based on µ-dominance concept and maxmin sorting scheme. Besides that, the paper also presents the results of the algorithm when it is used in the automated synthesis of optimum performance CMOS radio-frequency and microwave binary-weighted differential switched capacitor arrays (RFDSCAs). The genetic synthesis tool optimizes a fitness function which is based on the performance parameter of the RFDSCAs. To validate the proposed design methodology, a CMOS RFDSCA is synthesized, using a 0.25 ¼m BiCMOS technology.

A High-Performance Digitally Controlled LC Oscillator for Ku-Band Applications

A 13.5-15.5 GHz low phase noise digitally controlled LC VCO, designed in a 0.25 mum BiCMOS technology, is presented in this paper. The resonant circuit of the VCO uses a high performance radio-frequency differential binary-weighted switched capacitor array (RFDSCA) to cover the 2 GHz tuning band with a continuous tuning voltage of 5 V. The RFDSCA circuit was optimized using a new automated synthesis method in order to guarantee a VCO with minimum phase noise. The VCO presents a typical phase noise of -116 dB/Hz @ 1MHz and a maximum tuning sensitivity of 165 MHz/V. The VCO core works with a voltage supply of 3 V and has a current consumption of 5 mA. The results demonstrate the feasibility of implementing and using high performance RFDSCAs as digital tuning elements at operating frequencies up to tens of gigahertz.

High Performance Microstrip Bandpass Filters with Nonsymmetrical Parallel Coupled Lines

A new improved technique for the design of bandpass microstrip filters based on the image parameter concept is presented. Realizability is guaranteed by manufacturing constraints being incorporated into the design procedure. Passband limitations associated with a previous technique are circumvented by the use of nonsymmetrical parallel-coupled sections. Both computed and experimental results demonstrate excellent filter performance in terms of bandpass attenuation, associated with a reduced number of elements.

Design Optimization of Radio Frequency Discrete Tuning Varactors

This work presents a procedure to automate the design of Si-integrated radio frequency (RF) discrete tuning varactors (RFDTVs). The synthesis method, which is based on evolutionary algorithms, searches for optimum performance RF switched capacitor array circuits that fulfill the design restrictions. The design algorithm uses the *** -dominance concept and the maximin sorting scheme to provide a set of different solutions (circuits) well distributed along an optimal front in the parameter space (circuit size and component values). Since all the solutions present the same performance, the designer can select the circuit that is best suited to be implemented in a particular integration technology. To assess the performance of the synthesis procedure, several RFDTV circuits, provided by the algorithm, were designed and simulated using a

Design of Radio-Frequency Integrated CMOS Discrete Tuning Varactors Using the Particle Swarm Optimization Algorithm

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