Fernando Fortes

Test setup for error vector magnitude measurement on WLAN transceivers

This paper presents a measurement system and experimental examples of error vector magnitude measurements on a wireless local area network receiver under several radio frequency impairments, with emphasis to local oscillator phase noise. An algorithm that cancels the phase and frequency carrier synchronization error is presented. Typical base band figure of merit are obtained under influence of these impairments. The described method allows the experimental calculation of error vector magnitude without a dedicated vector analyzer.

A 5GHz/1.8V CMOS active balun integrated with LNA

An RF active balun integrated with LNA was presented. The total circuit is fully integrated in a low cost CMOS process with total area of 1mm2. Simulations show that under a 1.8V power supply the circuit has a 23 dB differential gain at 5 GHz with 8mA current consumption. The overall circuit presents a well balanced broadband behavior, since the balun exhibits low differential phase and magnitude errors. It also achieves better performance in S21, ldBCPO, OIP3 and power consumption.

A dual-band 1.7V CMOS variable gain low noise amplifier

The design and simulation of a dual-band monolithic low noise amplifier, with active balun and gain control integrated on the same die, is presented on this paper. The circuit includes an internal DAC, allowing sixteen gain levels with digital control. The fully integrated circuit was implemented in a 0.35 mum AMS CMOS standard technology and simulated with BSIM3 model. Simulations show a 16 dB (1 dB/step) dynamic gain variation in a 1.4-1.7 GHz band (includes dual sub-bands), a phase and transducer gain magnitude errors less than 1.6deg and 0.2 dB, respectively, a 1.24 dB noise figure and -23 dBm input-referred 1 dB compression point both at maximum gain, 50 Omega input and output match, while drawing less than 7.5 mA from a 1.7 V power supply, including analog and digital system.

A 5GHz/1.8V low power CMOS low-noise amplifier

This paper presents the design and implementation of a low power, low noise amplifier aimed at IEEE 802.11a for WLAN applications. It was designed to be integrated with an active balun and mixer, representing the first step toward a fully integrated monolithic WLAN receiver. All the required circuits are integrated at the same die and are powered by 1.8V supply source. Preliminary experimental results (S-parameters) are shown and promise excellent results.

A BiCMOS Low Voltage Power Amplifier for Wireless Communications

This paper describes the design and test of a low voltage monolithic power amplifier for DECT specifications. The circuit is implemented in a standard low power BiCMOS process but uses a non standard transistor structure. The standard transistor model was adjusted for this structure. The circuit has a die area of 0.52mm2 with an external output matching network. The amplifier was optimised for a 3V power supply operation.

A Monolithic 60GHz power amplifier with feedback stabilization

For personal communication systems, the highest possible integration into monolithic technology of all RF functions are desirable. For future mobile communication systems, one of the assigned bands is in the range of 60GHz. In this paper, the design and test of a monolithic power amplifier with 0.15¿m PMHFET technology is presented, which is targeted at an output power of 50mW at 62GHz and a minimum gain of 7dB. In order to choose the best FET bias, a nonlinear model for the PMHFETs based on continuous DC and AC measurements (C-model) was derived. To avoid stability problems, a RC feedback network for each device was introduced. For comparison purposes, the amplifier final version was simulated again using a nonlinear model based on pulsed measurements (P-model). Models for the microstrip discontinuities were obtained from EM simulations. Experiments on a 3mm × 4mm chip showed an output power of 16.5dBm at 62GHz, for an input power of 10dBm. A 1dB compression point of 15dBm was encountered.

Millimeter wave power amplifier with unconditionally stable devices

For portable communication terminals, power amplifiers on monolithic technology are needed. In this paper the design and test of a 60 GHz monolithic power amplifier is presented. The amplifier uses PMHFET monolithic technology with 0.15 micrometers mushroom gate length and microstrip structures. The chip size is 3mm X 1.5mm. For the amplifier design, a PMHFET nonlinear model based on continuous DC and AC measurements up to V-band was obtained. Models for some of the microstrip discontinuities were obtained from EM simulations. An output power greater than 100mW at 62GHz with more than 10dB gain was achieved. A power added efficiency of 16 percent was measured with VDS equals 2.5V.