Matthias Brandli

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology

As exemplified by standards such as OIF CEI-25G, 32G-FC, and next-generation 100GbE, serial link data rates are being pushed up to 25 to 28Gb/s in order to increase I/O system bandwidth. Such speeds represent a near doubling of the state-of-the-art for fully integrated transceivers [1-3]. With scaling no longer providing large gains in device speed, significant design advances must be made to attain these data rates. This paper describes a 28Gb/s serial link transceiver featuring a source-series terminated (SST) driver topology with twice the speed of existing designs, a two-stage peaking amplifier with capacitively-coupled parallel input stages and active feedback, and a 15-tap DFE. The use of capacitive level-shifters allows a single current-integrating summer to drive the parallel paths used for speculating the first two DFE taps.

4.7 A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm 2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS

For an on-chip or fully integrated microprocessor power-delivery system, the on-chip power converter must 1) be designed using the same technology as the microprocessor, 2) deliver high power density to supply a microprocessor core with small area overhead, 3) achieve high efficiency, and 4) perform fast regulation over a wide voltage range for dynamic voltage and frequency scaling (DVFS). On-chip switched-capacitor (SC) converters have gained increasing popularity for this application due to their ease of integration using only transistors and capacitors readily available in the chosen technologies [1-6].

A 4.6W/mm 2 power density 86% efficiency on-chip switched capacitor DC-DC converter in 32 nm SOI CMOS

The future trends in microprocessor supply current requirements represent a bottleneck for next generation high-performance microprocessors since the number of supply pins will constitute an increasingly larger fraction of the total number of package pins available. This leaves few pins available for signaling. On-chip power conversion is a means to overcome this limitation by increasing the input voltage - thereby reducing the input current - and performing the final power conversion on the chip itself. This paper details the design and implementation of on-chip switched capacitor converters in deep submicron technologies. High capacitance density deep trench capacitors with a low parasitic bottom plate capacitor ratio available in the technology facilitate high power density and efficiency in on-chip switched capacitor converter implementations. The measured performance of a 2 : 1 voltage conversion ratio on-chip switched capacitor converter implemented in 32nm SOI CMOS technology with 1.8V input voltage results in a power density of 4.6W/mm2 at 86% efficiency when operated at a switching frequency of 100MHz.

A 10 Gb/s 8-Tap 6b 2-PAM/4-PAM Tomlinson–Harashima Precoding Transmitter for Future Memory-Link Applications in 22-nm SOI CMOS

Tomlinson-Harashima (TH) precoding is a transmitter equalization technique in which the post-cursor intersymbol interference (ISI) is canceled by means of an infinite impulse response (IIR) filter with modulo (MOD)-based amplitude limitation. TH equalizers are suited for asymmetric links, such as DRAM interfaces, where the transmitter contains the equalization complexity and the receiver is kept simple. To increase the data rate, we propose the application of pipelining and half-rate operation to the ISI subtraction in the equalizers feedback path. A TH equalizer with 8 taps, 6 bit resolution, and 2-PAM/4-PAM support has been implemented in 22-nm silicon-on-insulator (SOI) CMOS technology. In measurements, the feedback delay reduction techniques allow us to equalize 34-cm-long PCB traces having 12-dB loss with 7 × ISI reduction for 5.0-Gb/s 2-PAM signaling, and in 10.0-Gb/s 4-PAM mode completely closed eye diagrams are opened. The measured efficiency of the 145 μm× 115 μm transmitter is 1.2 pJ/bit in 4-PAM mode at 5.0 Gbaud with disabled equalization and increases linearly with 14 μW/Gbaud per 1% increase of the equalization tap weights.

A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS

This paper describes a low-power implementation of a receiver data path, consisting of the RX termination with ESD, continuous-time linear equalizer (CTLE), and a 15-tap decision feedback equalizer (DFE) running at quarter rate. While the first 3 DFE taps are implemented by speculation, the latter 12 taps use a switched-cap (SC-DFE) approach. The circuit was produced in 32nm SOI-CMOS, and was measured to receive 30Gb/s PRBS31 data at <;10-12 BER over a 36dB loss channel with an energy efficiency of 3.1mW/Gbps.

Implementation of Low-Power 6–8 b 30–90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS

A model for voltage-based time-interleaved sampling is introduced with two implementations of highly interleaved analog-to-digital converters (ADCs) for 100 Gb/s communication systems. The model is suitable for ADCs where the analog input bandwidth is of concern and enables a tradeoff between different architectures with respect to the analog input bandwidth, the hold time of the sampled signal, and constraints on the clock path. The two ADCs at 6 and 8 b resolution implement inline demux sampling with 32χ and 64χ interleaving to achieve 36 GS/s at 110 mW and 90 GS/s at 667 mW, respectively. The analog input bandwidth of both ADCs exceeds 20 GHz. The SNDR of the 64χ interleaved ADC is above 36 dB up to 6.1 GHz and above 33 dB up to 19.9 GHz at 90 GS/s, and the SNDR of the 32χ interleaved ADC exceeds 31.6 dB up to Nyquist at 36 GS/s. The 32χ and 64χ interleaved ADCs are optimized for area and occupy 0.048 and 0.45 mm2, respectively, in 32 nm CMOS SOI technology.

A 10 W On-Chip Switched Capacitor Voltage Regulator With Feedforward Regulation Capability for Granular Microprocessor Power Delivery

Granular power delivery with per-core regulation for microprocessor power delivery has the potential to significantly improve the energy efficiency of future data centers. On-chip switched capacitor converters can enable such granular power delivery with per-core regulation given a high efficiency, high power density, fast response time, and high output power converter design. This paper details the implementation of an on-chip switched capacitor voltage regulator in a 32 nm SOI CMOS technology with deep trench capacitors. A novel feedforward control for reconfigurable switched capacitor converters is presented. The feedforward control reduces the output voltage droop following a transient load step. This leads to a reduced minimum microprocessor supply voltage, thereby reducing the overall power consumption of the microprocessor. The implemented on-chip switched capacitor voltage regulator provides a 0.7-1.1 V output voltage from 1.8 V input. It achieves a 85.1% maximum efficiency at 3.2 W/mm2 power density, a subnanosecond response time with improved minimum supply voltage capability, and a maximum output power of 10 W. For an output voltage of 850 mV, the feedforward control reduces the required voltage overhead by 60 mV for a transient load step from 10% to 100% of the nominal load. This can reduce the overall power consumption of the microprocessor by 7%.

A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth

A 16 Gb/s I/O link receiver fabricated in 22 nm CMOS SOI technology is presented. Attenuation and ISI of transmitted NRZ data across PCB channels are equalized with a CTLE feeding an 8-tap DFE. The first tap uses digital speculation and the following seven taps are realized by means of the switched-capacitor technique. Timing recovery and control are performed with a Mueller-Müller type-A baud-rate CDR. The architecture is half-rate and requires one phase rotator. In total, each slice has six comparators to recover data and timing information. The secondorder digital CDR operates at quarter-rate and features a low-latency implementation of the proportional path. At 16 Gb/s, 1 Vppd PRBS31 data transmitted without FFE equalization is recovered across a PCB channel with 34 dB attenuation at 8 GHz. The measured tracking bandwidth is 31 kppm (16 GHz ± 496 MHz), and an amplitude of 3 UIPP is tolerated at 1 MHz sinusoidal jitter. The sinusoidal jitter amplitude tolerance measured at 10 Gb/s is 0.4 UIPP at 10 MHz and remains above 0.2 UIPP up to 1 GHz with PRBS31 data recovered (BER <; 10-12) across a PCB channel with 27 dB attenuation at 5 GHz. The power efficiency is 3.7 mW/Gb/s, including the full-rate clock receiver.

Modeling and Pareto Optimization of On-Chip Switched Capacitor Converters

The operation and efficiency of on-chip switched-capacitor (SC) converters are highly affected by the parasitic bottom plate capacitor present in on-chip capacitor technologies. Existing modeling frameworks do not in a comprehensive manner take the effect of the bottom plate capacitor on converter operation and efficiency into account. This paper extends an existing SC state space modeling framework to include the bottom plate capacitor. The developed model is used in a Pareto optimization procedure to optimally select the component values of a 2:1 on-chip SC converter. Implemented in a 32 nm SOI CMOS technology that features the high-density deep trench capacitor, the on-chip converter achieves 86% maximum efficiency at 4.6 W/mm2 power density while converting from a 1.8 V input voltage to 830 mV output voltage.

A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os

In this paper, we present a digital equalizer for 16Gb/s backplane I/Os which consumes only 3.5pJ/bit for an 8-tap FFE and 4+4 tap DFE operation. Several design choices were chosen to enable low power consumption at high speed. First, the FFE leverages parallelism to lower the supply voltage, while the DFE runs from a higher supply to close the feedback loop. Second, the FFE uses distributed arithmetic to reduce the number of required additions. Third, the DFE taps leave a window of four equalizer taps, which are covered by the FFE, in order to close the timing. Finally, a custom digital design style was chosen, which enabled the optimization of critical blocks and wires. At 0.6V supply, the FFE was measured to consume 1pJ/bit, while the DFE consumes 1.6pJ/bit at 0.9V while running at 16Gb/s.