Luuk F. Tiemeijer

Low-Loss Patterned Ground Shield Interconnect Transmission Lines in Advanced IC Processes

In this paper, we provide an extensive experimental and theoretical study of the benefits of patterned ground shield interconnect transmission lines over more conventional layouts in advanced integrated-circuit processes. As part of this experimental work, we present the first comparative study taken on truly differential transmission line test structures. Our experimental results obtained on transmission lines with patterned ground shields are compared against a predictive compact equivalent-circuit model. This model employs exact closed-form expressions for the inductances, and describes key performance figures such as characteristic impedance and attenuation loss with excellent accuracy

Test structure design considerations for RF-CV measurements on leaky dielectrics

We present an MOS capacitance-voltage measurement methodology that, contrary to present methods, is highly robust against gate leakage current densities up to 1000 A/cm/sup 2/. The methodology features specially designed RF test structures and RF measurement frequencies. It allows MOS parameter extraction in the full range of accumulation, depletion, and inversion.

RF-Noise Modeling in Advanced CMOS Technologies

RF circuit design in deep-submicrometer CMOS technologies relies heavily on accurate modeling of thermal noise. Based on Nyquists law, predictive modeling of thermal noise in MOSFETs was possible for a long time, provided that parasitic resistances and short-channel effects were properly accounted for. In sub-100-nm technologies, however, microscopic excess noise starts to play a significant role and its incorporation in thermal noise models is unavoidable. Here, we will review several crucial ingredients for accurate RF noise modeling, with emphasis on sub-100-nm technologies. In particular, a detailed derivation and discussion are presented of our microscopic excess noise model. It is shown to qualitatively explain the observed noise (across bias and geometry) in a wide range of commercially available sub-100-nm foundry processes. Besides, the impact of excess noise on the minimum noise figure is discussed.

Analysis, Design, Modeling, and Characterization of Low-Loss Scalable On-Chip Transformers

A few important design choices for a low-loss scalable on-chip transformer are discussed, the most important one being that the capacitive and inductive couplings should be aligned to minimize insertion loss. The importance of these design choices is illustrated both theoretically as well as experimentally. In particular, for the first time the performance of these on-chip transformers is verified with four-port S -parameter measurements taken up to 67 GHz. With that, an insertion loss of only 0.6 dB up to 30 GHz is demonstrated. To facilitate the use of these low-loss on-chip transformers in the RF integrated-circuit design flow, a scalable compact equivalent-circuit model suitable for all pre-layout circuit simulations is described, which accurately predicts transformation ratios, transmission efficiencies and balun amplitude and phase imbalances.

The effect of copper design rules on inductor performance

In this paper, the effect of process-related design rules on inductor performance are shown. In advanced processes the copper line width is limited, and the metal pattern density must be as uniform as possible. The results obtained on inductors fabricated in-one metal layer with a different number of parallel tracks, with and without copper tiles are presented. The geometry and the orientation of the tiles are also varied. The comparison allows us to quantify the influence of copper tiles on the inductor quality factor.

Experimental Demonstration and Modeling of Excess RF Noise in Sub-100-nm CMOS Technologies

Accurate modeling of thermal noise in MOSFETs is crucial for RF application of deep-submicrometer CMOS technologies. Here, we present RF noise measurements on four commercial advanced CMOS technologies down to the 45-nm node. Based on this extensive set of measurements, we prove the existence of excess noise (i.e., above the pure Nyquist level), but at the same time, we show that it is significant only for sub-100-nm MOSFETs. The amount of excess noise depends mainly on the channel length, and its occurrence is remarkably universal across technologies. We also present an electric-field-dependent extension of Nyquists law that represents a nonequilibrium-transport correction to diffusive transport. We show that this microscopic model quantitatively explains the main features of the experimentally observed excess noise for all technologies. This includes its bias dependence, its geometrical scaling behavior, and the observed difference between n-channel and p-channel devices.

On the Accuracy of the Parameters Extracted From

In this paper, we compare the accuracy of the telegraphers equation transmission line parameters extracted with different methods from deembedded S-parameter measurements taken on differential integrated circuit transmission lines. We present a mathematical proof that conventional ldquoopen-shortrdquo deembedding is sufficient to extract the intrinsic propagation constant gamma of the transmission line, but that at the same time, some deembedding errors will remain for the extracted characteristic impedance Z 0. We illustrate this by comparing experimental results obtained after ldquoopen-shortrdquo and ldquoshort-openrdquo deembedding, and explain that as a result of this, using either known capacitance/known conductance or known inductance/known resistance approximations to study the remaining transmission line parameters can be attractive.

S

A predictive causal physics-based compact model that describes the electrical behavior of multiple bond wires as a function of signal frequency and geometry of the wires is presented. It takes into account the inductive coupling between the wires, the frequency-dependent losses, and the capacitance between the wires and the ground plane. The model does not require any fitting parameters and places no restriction on the shape of the bond wires. Model predictions of resistance, of capacitance to the ground plane, and of self and mutual inductances of bond wires with different shapes were compared to the corresponding measured quantities. All inductive calculations use closed formulas that give a better approximations than the state-of-the-art. Furthermore, the causal nature of this model implies that it may be used for time-domain simulations.

-Parameter Measurements Taken on Differential IC Transmission Lines

In this paper, we report a systematic and efficient approach to obtain lumped-element models for differential integrated-circuit interconnect transmission lines covering both the low-frequency R/C as well as the high-frequency quasi-TEM behavior. To accurately model signal delay and loss, and to preserve causality, the frequency dependence of both line resistance as well as the line inductance is included in our model. The impact of ground inductance is also properly covered by the model. The validity of our approach is verified against experimental data collected up to 120 GHz for the even and odd modes on these differential transmission lines. We predict that these lines can transport data over 1-cm distance with rates up to 40 Gb/s, even with some imbalance in differential drive.

A Physics-Based Causal Bond-Wire Model for RF Applications

For the first time, the effects of poly depletion on the RF noise performance of advanced CMOS transistors are reported and analyzed. Based on measurements and physical device simulations we quantify the increasing danger of poly gate depletion with downscaling on the RF noise parameters of CMOS devices. While poly depletion does not affect the minimum noise figure, it results in a degradation of the noise matching freedom for RFIC designers. This trend worsens with technology downscaling.