G.D.J. Smit

PSP: An Advanced Surface-Potential-Based MOSFET Model for Circuit Simulation

This paper describes the latest and most advanced surface-potential-based model jointly developed by The Pennsylvania State University and Philips. Specific topics include model structure, mobility and velocity saturation description, further development and verification of symmetric linearization method, recent advances in the computational techniques for the surface potential, modeling of gate tunneling current, inclusion of the retrograde impurity profile, and noise sources. The emphasis of this paper is on incorporating the recent advances in MOS device physics and modeling within the compact modeling context

Benchmark Tests for MOSFET Compact Models With Application to the PSP Model

This paper presents the results of several qualitative ldquobenchmarkrdquo tests that were used to verify the physical behavior of the PSP model and its usefulness for future generations of CMOS IC design. These include newly developed tests and new experimental data stemming from low-power, RF, mixed-signal, and analog applications of MOSFETs.

PSP-based compact FinFET model describing dc and RF measurements

We present a new, PSP-based compact model for symmetric 3-terminal FinFETs with thin undoped or lightly doped body, which is suitable for digital, analog, and RF circuit simulation. The model is surface potential based and is demonstrated to accurately describe both TCAD data and measured FinFET currents, conductances, and capacitances

The Physical Background of JUNCAP2

A new physics-based junction model for CMOS, called JUNCAP2, is presented. It contains new single-piece formulations for the Shockley-Read-Hall generation/recombination current and the trap-assisted tunneling (TAT) current, which are valid both in forward and reverse mode of operation. Moreover, the TAT model extends the existing model (IEEE Trans. Electron Devices, vol. 39, p. 2090, 1992) to the high electric fields encountered in todays CMOS technologies. Furthermore, the model contains expressions for junction capacitance, ideal current, band-to-band tunneling current, avalanche breakdown, and junction shot noise. The parameter extraction is also discussed in this paper

RF-Noise Modeling in Advanced CMOS Technologies

RF circuit design in deep-submicrometer CMOS technologies relies heavily on accurate modeling of thermal noise. Based on Nyquists law, predictive modeling of thermal noise in MOSFETs was possible for a long time, provided that parasitic resistances and short-channel effects were properly accounted for. In sub-100-nm technologies, however, microscopic excess noise starts to play a significant role and its incorporation in thermal noise models is unavoidable. Here, we will review several crucial ingredients for accurate RF noise modeling, with emphasis on sub-100-nm technologies. In particular, a detailed derivation and discussion are presented of our microscopic excess noise model. It is shown to qualitatively explain the observed noise (across bias and geometry) in a wide range of commercially available sub-100-nm foundry processes. Besides, the impact of excess noise on the minimum noise figure is discussed.

Best Practices for Compact Modeling in Verilog-A

Verilog-A is the de facto standard language that the semiconductor industry uses to define compact models. Unfortunately, it is easy to write models poorly in Verilog-A, and this can lead to unphysical model behavior, poor convergence, and difficulty in understanding and maintaining model codes. This paper details best practices for writing compact models in Verilog-A, to try to help raise the quality of compact modeling throughout the industry.

PSP-SOI: A Surface Potential Based Compact Model of Partially Depleted SOI MOSFETs

This paper reports recent progress on partially depleted (PD) SOI modeling using a surface potential based approach. The new model, called PSP-SOI, is formulated within the framework of the latest industry standard bulk MOSFET model PSP. In addition to its physics-based formulation and scalability inherited from PSP, PSP-SOI captures SOI specific effects by including a floating body simulation capability, a parasitic bipolar model, and self-heating. A nonlinear body resistance is included for modeling body-contacted SOI devices. The PSP-SOI model has been extensively tested on several PD/SOI technologies.

Benchmarking the PSP Compact Model for MOS Transistors

Recently, the PSP model was selected as the first surface-potential-based industry standard compact MOSFET model. This work presents the results of several qualitative benchmark tests that over the last two years were used to verify the physical behavior of the new model and its usefulness for future generations of CMOS IC design. These include newly developed tests and previously unavailable experimental data stemming from low-power, RF, mixed-signal, and analog applications of MOSFETs.

A Compact Model for Valence-Band Electron Tunneling Current in Partially Depleted SOI MOSFETs

The valence-band electron (EVB) tunneling current in partially depleted silicon-on-insulator (SOI) MOSFETs increases as the gate oxide gets thinner and affects the dynamic behavior of devices and circuits. We present an engineering model of EVB tunneling current based on the surface-potential formulation. The new model is implemented in a SOI MOSFET compact model and is used to study the impact of EVB tunneling on circuit performance. Simulations of stacked logic gates show that the EVB tunneling current not only boosts circuit switching speed but also mitigates the history dependence of propagation delays

Experimental Demonstration and Modeling of Excess RF Noise in Sub-100-nm CMOS Technologies

Accurate modeling of thermal noise in MOSFETs is crucial for RF application of deep-submicrometer CMOS technologies. Here, we present RF noise measurements on four commercial advanced CMOS technologies down to the 45-nm node. Based on this extensive set of measurements, we prove the existence of excess noise (i.e., above the pure Nyquist level), but at the same time, we show that it is significant only for sub-100-nm MOSFETs. The amount of excess noise depends mainly on the channel length, and its occurrence is remarkably universal across technologies. We also present an electric-field-dependent extension of Nyquists law that represents a nonequilibrium-transport correction to diffusive transport. We show that this microscopic model quantitatively explains the main features of the experimentally observed excess noise for all technologies. This includes its bias dependence, its geometrical scaling behavior, and the observed difference between n-channel and p-channel devices.