Andries J. Scholten

PSP-based compact FinFET model describing dc and RF measurements

We present a new, PSP-based compact model for symmetric 3-terminal FinFETs with thin undoped or lightly doped body, which is suitable for digital, analog, and RF circuit simulation. The model is surface potential based and is demonstrated to accurately describe both TCAD data and measured FinFET currents, conductances, and capacitances

Impact of process scaling on 1/f noise in advanced CMOS technologies

The influence of the gate-oxide thickness, the substrate dope, and the gate bias on the input-referred spectral 1/f noise density Sv/sub gate/ has been experimentally investigated. It is shown that the dependence on the oxide thickness and the gate bias can be described by the model of Hung, and that Sv/sub gate/ can be predicted for future technologies. Discrepancies with the ITRS roadmap are discussed.

RF-Noise Modeling in Advanced CMOS Technologies

RF circuit design in deep-submicrometer CMOS technologies relies heavily on accurate modeling of thermal noise. Based on Nyquists law, predictive modeling of thermal noise in MOSFETs was possible for a long time, provided that parasitic resistances and short-channel effects were properly accounted for. In sub-100-nm technologies, however, microscopic excess noise starts to play a significant role and its incorporation in thermal noise models is unavoidable. Here, we will review several crucial ingredients for accurate RF noise modeling, with emphasis on sub-100-nm technologies. In particular, a detailed derivation and discussion are presented of our microscopic excess noise model. It is shown to qualitatively explain the observed noise (across bias and geometry) in a wide range of commercially available sub-100-nm foundry processes. Besides, the impact of excess noise on the minimum noise figure is discussed.

Impact of interface states on MOS transistor mismatch

Based on modified 2-D drift-diffusion device simulations, mismatch signatures and principal component analysis, this study proves that random interface states fluctuating in terms of density, position and energy levels, in addition to random dopant fluctuations are required for proper interpretation of drain current mismatch in contemporary CMOS technologies.

Best Practices for Compact Modeling in Verilog-A

Verilog-A is the de facto standard language that the semiconductor industry uses to define compact models. Unfortunately, it is easy to write models poorly in Verilog-A, and this can lead to unphysical model behavior, poor convergence, and difficulty in understanding and maintaining model codes. This paper details best practices for writing compact models in Verilog-A, to try to help raise the quality of compact modeling throughout the industry.

PSP-SOI: A Surface Potential Based Compact Model of Partially Depleted SOI MOSFETs

This paper reports recent progress on partially depleted (PD) SOI modeling using a surface potential based approach. The new model, called PSP-SOI, is formulated within the framework of the latest industry standard bulk MOSFET model PSP. In addition to its physics-based formulation and scalability inherited from PSP, PSP-SOI captures SOI specific effects by including a floating body simulation capability, a parasitic bipolar model, and self-heating. A nonlinear body resistance is included for modeling body-contacted SOI devices. The PSP-SOI model has been extensively tested on several PD/SOI technologies.

Experimental Demonstration and Modeling of Excess RF Noise in Sub-100-nm CMOS Technologies

Accurate modeling of thermal noise in MOSFETs is crucial for RF application of deep-submicrometer CMOS technologies. Here, we present RF noise measurements on four commercial advanced CMOS technologies down to the 45-nm node. Based on this extensive set of measurements, we prove the existence of excess noise (i.e., above the pure Nyquist level), but at the same time, we show that it is significant only for sub-100-nm MOSFETs. The amount of excess noise depends mainly on the channel length, and its occurrence is remarkably universal across technologies. We also present an electric-field-dependent extension of Nyquists law that represents a nonequilibrium-transport correction to diffusive transport. We show that this microscopic model quantitatively explains the main features of the experimentally observed excess noise for all technologies. This includes its bias dependence, its geometrical scaling behavior, and the observed difference between n-channel and p-channel devices.

A physics-based RTN variability model for MOSFETs

Low Frequency Noise (LFN) and Random Telegraph Noise (RTN) are performance limiters in many analog and digital circuits. For small area devices the noise PSD can easily vary by more than 4 orders of magnitude, imposing serious threat in circuit performance and possibly reliability. In this paper we propose a new RTN/LFN variability area scaling model. The model is validated through numerous experimental results for n-channel and p-channel devices from different CMOS nodes. Using this model we demonstrate that the variability found in our measurements can be explained using reasonable physical quantities and we clarify why variability, σ[log(SId)], of RTN/LFN doesnt follow a 1/√area dependency.

A Physics-Based Statistical RTN Model for the Low Frequency Noise in MOSFETs

In this paper, we develop a statistical model for random telegraph noise (RTN) related low-frequency noise (LFN). With our proposed model, one can calculate the expected value and the variability of the noise as a function of bias and device parameters. We clarify why the variability of RTN/LFN does not follow a 1/√area dependence. The model explains the effect of the halo implanted regions on the LFN statistics and the large variability of long channel devices found under certain bias conditions, which can be as large as that of short channel devices. We show that the LFN of n-channel and p-channel MOSFETs can be described by the same mechanism. From our results, we derive that the trap density of the p-channel device is a strongly varying function of the Fermi level, whereas for the n-channel the trap density can be considered constant. We validate the model through numerous experimental results from different CMOS nodes, down to 40 nm. We also demonstrate that the noise, and its variability, found in our measurements can be modeled using reasonable physical quantities.

Comparison of electrical techniques for temperature evaluation in power MOS transistors

Three electrical techniques (pulsed-gate, AC-conductance and sense-diode) for temperature evaluation in power MOS transistors have been experimentally compared on the same device. The device under test is a silicon-on-insulator (SOI) laterally-diffused MOSFET (LDMOS) design with embedded sense-diodes in the center and at the edge of the device for providing local temperature information. On-wafer measurements have been performed on a thermal chuck in the temperature range 25-200°C to extract self-heating information and predict the junction temperature for different biasing conditions. Good agreement (within 10%) between the different techniques is achieved, evidencing that reliable temperature estimations can be made using each of the proposed electrical techniques. As a result, factors other than experimental accuracy will play a role in the choice of the most adequate technique for the application of interest. Guidelines for this choice are provided in a benchmarking analysis accounting for ease of application, temperature calibration and accuracy of the results.