Luz Balado

Verifying Functional Specifications by Regression Techniques on Lissajous Test Signatures

In this paper, a low-cost method to verify functional specifications of analog VLSI circuits is proposed. The method is based on the analysis of Lissajous signatures combined with regression techniques. In order to obtain Lissajous signatures, the observation space is partitioned into zones using hyperplanes, and a set of integer values used as the digital signature of the circuit is generated by Lissajous curve zone crossings. A predictor function obtained by nonlinear regression techniques predicts the functional specification parameters of the circuit under consideration. The viability of this methodology is analyzed and applied to verify the center frequency f 0 of a bandpass biquad filter. Experimental measurements show an accurate prediction of the center frequency of the designed filter.

Testing Biquad Filters under Parametric Shifts Using X-Y Zoning

Testing mixed-signal circuits is a difficult task due to defect modeling challenges, observability and controllability restrictions and ATE bandwidth limitations. In this paper, the X-Y Zoning test of a Biquad filter is addressed to select the optimal excitation frequency and the best partition of the X-Y plane. Thus we obtain the best sensitivity of the BIST scheme to parametric shifts of the parameters defining the filter. The study has been particularized to shifts in the natural frequency f0 of the Biquad filter. Analytical results on the best input as well as the best partition of the observed X-Y Lissajous plots are obtained. Extensive MATLAB simulations validate the proposal, which has also been validated experimentally. For these experiments, multiple implementations of the Biquad with nominal and shifted parameters have been performed using a commercial Field Programmable Analog Array (FPAA). The experimental measures show good correlation with the analytical expressions and the simulations performed, and validate the proposed testing methodology.

M-S test based on specification validation using octrees in the measure space

Testing M-S circuits is a difficult task demanding high amount of resources. To overcome these drawbacks, indirect testing methods have been adopted as an efficient solution to perform specification based tests using easy to measure metrics. In this work, a testing technique using octrees in the measure space is presented. Octrees have been used in computer graphics with successful results for rendering, image processing and space clustering applications. In this paper are used to encode the test acceptance region with arbitrary precision after an statistical training phase. Such representation allows an efficient way to test a candidate circuit in terms of test application time. The method is applied to test a Biquad filter with encouraging results. Test escapes and test yield loss caused by parametric variations have been estimated.

Analog circuit test based on a digital signature

Production verification of analog circuit specifications is a challenging task requiring expensive test equipment and time consuming procedures. This paper presents a method for low cost on-chip parameter verification based on the analysis of a digital signature. A 65 nm CMOS on-chip monitor is proposed and validated in practice. The monitor composes two signals (x(t), y(t)) and divides the X-Y plane with nonlinear boundaries in order to generate a digital code for every analog (x, y) location. A digital signature is obtained using the digital code and its time duration. A metric defining a discrepancy factor is used to verify circuit parameters. The method is applied to detect possible deviations in the natural frequency of a Biquad filter. Simulated and experimental results show the possibilities of the proposal.

Efficient Production Binning Using Octree Tessellation in the Alternate Measurements Space

Binning after volume production is a widely accepted technique to classify fabricated integrated circuits (ICs) into different clusters depending on different degrees of specification compliance. This allows the manufacturer to sell nonoptimal devices at lower rates, so adapting to customers quality-price requirements. The binning procedure can be carried out by measuring every single circuit performances, but this approach is costly and time-consuming. On the contrary, if alternate measurements are used to characterize the bins, the procedure is considerably enhanced. In such a case, the specification bin boundaries become arbitrary shape regions due to the highly nonlinear mappings between the specifications space and the alternate measurements space. The binning strategy proposed in this paper functions with the same efficiency regardless of these shapes. The digital encoding of the bins in the alternate measurements space using octrees is the key idea of the proposal. The strategy has two phases: 1) the training phase and 2) the binning phase. In the training phase, the specification bins are encoded using octrees. This first phase requires sufficient samples of each class to generate the octree under realistic variations, but it only needs to be performed once. The binning phase corresponds to the actual production binning of the fabricated ICs. This is achieved by evaluating the alternate measurements in the previously generated octree. The binning phase is fast due to the inherent sparsity of the octree data structure. In order to illustrate the proposal, the method has been applied to a band-pass Butterworth filter considering three specification bins as a proof of concept. Successful simulation results are reported showing considerable advantages as compared to a support vector machine (SVM)-based classifier. Similar bin misclassifications are obtained with both methods, 1.68% using octrees and 1.83% using SVM, while binning time is 5x faster using octrees than using the SVM-based classifier.

Analog Switches in programmable analog devices: quiescent defective behaviour

Analog Switches (AS) play an essential role in a large number of Mixed-Signal circuits. Depending on the use of AS, designers have optimised their topology to meet the needs of each specific switching function. Furthermore, the success of Field Programmable devices in the digital domain (FPGAs) has motivated some manufacturers to explore similar solutions to fast prototype in the Analog and Mixed Signal domains. In this work, we explore the defective behaviours of programmable AS under realistic catastrophic and parametric defects. A classification of the DC defective behaviours for bridging and open defects is presented. This classification shows that the simple fault model with faulty state of permanently transistor “stuck-on” or “stuck-off” is not sufficient to reflect the real behaviour of a defective switch. It has also been found that parametric defects such as threshold voltage variations are not DC testable, and would therefore require additional AC tests.

M-S specification binning based on digitally coded indirect measurements

Binning of IC circuits after volume fabrication is widely used to separate tested circuits in different classes depending on different degrees of specifications compliance. When the specifications are directly measured, the boundaries of the classes are usually linear functions in the specification space. For alternate testing strategies the indirect measures generate more complicated regions in the measure space due to the non linear mapping between the specification space and the measure space. The binning strategy proposed in this paper works with the same efficiency regardless of the shape of the boundaries of each binning region. A digital encoding of the measure space using octrees is the key idea of the proposal. The strategy has two phases: (1) The training to generate the digital codes for the binning subsets and (2) the actual production binning of the fabricated ICs. The first phase is performed only once and requires sufficient samples of each binning class to generate the octree under realistic variations. The second phase is fast and requires only to evaluate the octree using the measures of the tested IC. In order to illustrate the proposal, the method has been applied to a Biquad filter considering three specification bins as a proof of concept. Successful simulation results are reported showing considerable advantages in terms of binning speed. In addition, the method has been compared to a SVM classifier revealing substantial benefits.

Quality metrics for mixed-signal indirect testing

Analog and mixed-signal circuit testing is a challenging task demanding large amounts of resources. In order to battle against this drawback, alternate testing has been established as an efficient way of testing analog and M-S circuits by using indirect measures instead of the classic specification based testing. In this work we propose the use of Kendalls Tau rank correlation coefficient for rating the suitability of a set of candidate indirect measures to be used in mixed-signal testing. Such criterion is shown to be adequate since it allows to avoid or minimize information redundancy in the measures set. As a proof of concept, a 4th order band-pass Butterworth filter has been simulated under the presence of process variations. The circuit has been tested using a subset of measures selected according to minimum Kendalls Tau coefficient. Analog test efficiency metrics are reported showing test misclassification rate is among the best 15% possible, therefore validating the proposal.

Indirect test of M-S circuits using multiple specification band guarding ☆

Testing analog and mixed-signal circuits is a costly task due to the required test time targets and high end technical resources. Indirect testing methods partially address these issues providing an efficient solution using easy to measure CUT information that correlates with circuit performances. In this work, a multiple specification band guarding technique is proposed as a method to achieve a test target of misclassified circuits. The acceptance/rejection test regions are encoded using octrees in the measurement space, where the band guarding factors precisely tune the test decision boundary according to the required test yield targets. The generated octree data structure serves to cluster the forthcoming circuits in the production testing phase by solely relying on indirect measurements. The combined use of octree based encoding and multiple specification band guarding makes the testing procedure fast, efficient and highly tunable. The proposed band guarding methodology has been applied to test a band-pass Butterworth filter under parametric variations. Promising simulation results are reported showing remarkable improvements when the multiple specification band guarding criterion is used.

Improving indirect test efficiency using multi-directional tessellations in the measure space

Indirect test strategies have risen as a promising solution to overcome the challenges encountered in analog and mixed-signal circuit testing and the ever increasing device verification costs. This work explores the possibilities of using multidirectional tessellations in the indirect measure space aiming to reduce false positive test outcomes. The key idea of the proposal is to use several rotated 2n-ary trees in order to tessellate and encode the indirect measure space along multiple directions. Such tessellations create a refinement in the highly non linear test decision boundary without the need of including more circuit samples within the training set. The trained trees, together with a strict test decision criterion, serve as a classifier during the production testing phase. The proposed multi-directional tessellation methodology has been applied to test a Biquad filter under the presence of parametric variations. Promising simulation results report considerable improvements in lowering test escape metrics by an average factor of 50 as compared to a single octree tessellation as well as low computational overhead.