Rosa Rodríguez-Montañés

CURRENT VS. LOGIC TESTING OF GATE OXIDE SHORT, FLOATING GATE AND BRIDGING FAILURES IN CMOS

Logic testing has s o m e well known l imi ta t ions f o r circuits with failures causing intermediate voltage levels or, even , correct logic outputs with parametric deuiat ions f r o m the fault free specificattons. For these failures current testing might be considered as a complementary technique t o logic testing. I n this work, these physical defects widely encountered i n ioday’s CMOS processes, are modelled taking into account t h e topology o f the defective circuit and the parameters o f the technology used. These models are used to simulate a t electrical level (SPICE) the behaviour of a simple three inver ter chain wi th a f au l t y inverter. T h e merits o f current testing in f ront of voltage testing are studied for the classes of defects modelled.

Experimental Characterization of CMOS Interconnect Open Defects

Open defects have been intentionally designed in a set of interconnect metal lines. In order to improve the controllability and the observability of the experimental design, a simple bus structure with a scan register followed by a hold register is used to manage the set of interconnect lines. The strength of the open defects has been varied within a realistic range of resistances ranging from a full (complete) open to a weak (low resistance) open by means of broken metal lines and transmission gates, respectively. Experiments performed with an automatic test equipment show the influence of coupling capacitances with adjacent lines on the electrical behavior of the defective line. Furthermore, experimental evidence of the history effect on the delay caused by resistive opens is investigated. Validation of the measured results by means of theoretical as well as simulation analysis is presented. Finally, some recommendations to generate stuck-at, IDDQ and delay test are discussed in order to improve the detectability of such defects.

Quiescent current analysis and experimentation of defective CMOS circuits

Physical defects widely encountered in todays CMOS processes (bridges, gate oxide short (gas) and floating gates) are modeled taking into account the topology of the defective circuit and the parameters of the technology. These models are used to simulate at electrical level the behavior of a simple 3-inverter chain with a defective inverter. The results are compared with experimental data of integrated circuits fabricated with intentional defects. The influence of the characteristics of each defect on IDDQ has been investigated by electrical simulation and experimentation.

Analysis of bridging defects in sequential CMOS circuits and their current testability

Differences between controllability conditions for I/sub DDQ/ detectability iy in CMOS combinational and sequential circuits with bridging defects are presented. The usual detectability condition for current testability of bridges in combinational circuits is shown to fail for defective sequential circuits. A special class of bridges involving memory elements may change the state memorized in the element becoming current undetectable. Conditions for their occurrence have been investigated and their dependence on transistor size ratio and bridge resistance analyzed. A typical scan cell has been studied and its realistic bridges modifying the memorized state, identified.<<ETX>>

Diagnosis of Full Open Defects in Interconnecting Lines

A proposal for enhancing the diagnosis of full open defects in interconnecting lines of CMOS circuits is presented. The defective line is first classified as fully opened by means of a logic-based diagnosis tool (Faloc). The proposal is based on the division of the defective line into a number of segments. The selected group of segments is derived from the topology of the line and its surrounding circuitry. The logical information related to the neighbouring metal lines for each considered test pattern is taken into account. With the proposed diagnosis methodology, a set of likely locations for the open defect on the line is obtained. A ranking between the set of possible locations is presented based on the analysis of the quiescent current consumption of the circuit under test. Examples are presented in which the use of the diagnosis methodology is shown to discriminate between different locations of the full open defect.

Bridging defects resistance in the metal layer of a CMOS process

The resistance value of bridging defects in CMOS VLSI circuits are evaluated through a set of measurements performed on process-related defect monitoring wafers. The monitor circuits considered are made of metal1 lines. The results show how the vast majority of the measured metal1 to metal1 bridges has a low resistance. Only a small percentage of the overall bridges resulted in a resistance value above 500 Ω, while the exact percentage can vary from batch to batch. This high resistance does not seem to be the result of the material of the defect itself, since all these bridging defects were found to be caused by extra aluminium. The shape and location of the defect seem to be the cause of the high resistance values probably caused by poor contacts between the extra metal and the designed monitor lines.

I DDQ testing: state of the art and future trends

Abstract Quality assurance in electronic components and systems requires effective test strategies to be applied to ICs of increasing complexity and size. The traditional voltage techniques based on logic observation of the outputs have been found insufficient to guaranty the low defect escape requirements of growing sectors of IC users. This fact has motivated the search for complementary testing techniques which try to detect defects escaping logic testing. This paper attempts to explore the state of the art and the perspective of the test based on the observation of the quiescent current consumption of the IC, generally known as I DDQ testing. After introducing the basic principle of the technique and the components of the quiescent current in CMOS technologies, the physical defects which cause an increase of the I DDQ are presented. The state of the art of the detection of circuits with sensor(s) located on-chip (BICS) and off-chip is explored. A literature review of the circuits to sense the quiescent current permits their classification according to their function and structure. The different techniques to generate the input vectors to force the increase in quiescent current consumption are presented and, as an example, an ATPG to detect bridging faults is presented in detail. Finally the future trends of I DDQ testing are discussed taking into account the implications of scaling in CMOS. As the power supply voltage is reduced to maintain the electric fields in the MOS transistors and the global power consumption, the threshold voltages of the devices need to be lowered to maintain or increase the speed of the logic. As a consequence, the quiescent current consumption, I DDQ , increases exponentially. This fact decreases the discriminability of nondefective in front of defective quiescent currents. On the other hand, techniques to reduce the leakage currents are becoming available thanks to an active research effort directed mainly to decrease the quiescent power consumption in submicron ICs.

Estimation of the defective I/sub DDQ/ caused by shorts in deep-submicron CMOS ICs

The defective I/sub DDQ/ in deep-submicron full complementary MOS circuits with shorts is estimated. High performance and also low power scenarios are considered. The technology scaling, including geometry reductions of the transistor dimensions, power supply voltage reduction, carrier mobility degradation and velocity saturation, is modeled. By means of the characterization of the saturation current of a simple MOSFET, a lower bound of I/sub DDQ/ defective consumption versus L/sub eff/ is found. Quiescent current consumption lower bound for shorts intragate, and shorts intergate affecting at least one logic node is evaluated. The methodology is used to estimate the I/sub DDQ/ distribution, for a given input vector, of defective circuits. This I/sub DDQ/ estimation allows the determination of the threshold value to be used for the faulty/fault-free circuit classification.

Diagnosis of full open defects in interconnect lines with fan-out

The development of accurate diagnosis methodologies is important to solve process problems and achieve fast yield improvement. As open defects are common in CMOS technologies, accurate diagnosis of open defects becomes a key factor. Widely used interconnect full open diagnosis procedures are based on the assumption that neighbouring lines determine the voltage of the defective line. However, this assumption decreases the diagnosis efficiency for opens in interconnect lines with fan-out, when the influence of transistor capacitances becomes important. This work presents a diagnosis methodology for interconnect full open defects where the impact of transistor parasitic capacitances is included. The methodology is able to properly diagnose interconnect opens with fan-out even in the presence of Byzantine behaviour. Diagnosis results for real defective devices from different technology nodes are presented.

Delay caused by resistive opens in interconnecting lines

An accurate electrical fault characterization is required for the correct diagnosis and localization of CMOS interconnect defects. It has been traditionally accepted that a resistive open defect located at the beginning of an interconnecting line causes the maximum possible delay. The first-order approximation is sufficient to model the behaviour of high resistive opens. However, in this paper it is shown that low resistive opens do not follow this behaviour. In these cases, a second-order model is required for a more precise prediction of their defective behaviour, since the maximum delay is obtained for an intermediate location, which depends on the relationship between the open resistance, the on-resistance of the transistor network driving the defective net, the parasitic capacitances and the threshold voltage of the transistors driven by the defective net. For that purpose, an experimental circuit has been designed and fabricated where open defects have been intentionally added in a set of interconnect CMOS lines. Both simulation and experimental results on defective interconnect lines show maximum delays for opens located at intermediate positions provided that the resistance of the open is on the order of the on-resistance of the driving transistor network.