Lynn A. Abelson

Superconductor integrated circuit fabrication technology

Todays superconductor integrated circuit processes are capable of fabricating large digital logic chips with more than 10 K gates/cm/sup 2/. Recent advances in process technology have come from a variety of industrial foundries and university research efforts. These advances in processing have reduced critical current spreads and increased circuit speed, density, and yield. On-chip clock speeds of 60 GHz for complex digital logic and 750 GHz for a static divider (toggle flip-flop) have been demonstrated. Large digital logic circuits, with Josephson junction counts greater than 60 k, have also been fabricated using advanced foundry processes. Circuit yield is limited by defect density, not by parameter spreads. The present level of integration is limited largely by wiring and interconnect density and not by junction density. The addition of more wiring layers is key to the future development of this technology. We describe the process technologies and fabrication methodologies for digital superconductor integrated circuits and discuss the key developments required for the next generation of 100-GHz logic circuits.

An improved NbN integrated circuit process featuring thick NbN ground plane and lower parasitic circuit inductances

We report on the development of a 10 K, NbN superconductive integrated circuit (IC) technology that utilizes an improved SiO/sub 2/ interlevel dielectric (ILD) deposition process and a thick NbN ground plane layer to reduce parasitic circuit inductances. The ILD process uses a novel low frequency (40 kHz) substrate bias during sputter deposition of SiO/sub 2/, which produces very smooth oxide films having a roughness less than 0.1 nm (rms) as measured by atomic force microscopy (AFM). Bias-sputtered SiO/sub 2/ is used to planarize and to smooth the surface of the NbN ground plane layer in preparation for fabrication of NbN/MgO/NbN tunnel junctions. High current density tunnel junctions ranging from 1000 A/cm/sup 2/ to 5000 A/cm/sup 2/, fabricated over NbN ground planes up to 1 /spl mu/m thick, exhibit low subgap leakage (V/sub m//spl sim/15 mV at 10 K) and high subgap voltage (V/sub g/=4.4 mV at 10 K). Typical wiring inductance over ground plane has been reduced by 25% compared to our present NbN foundry process.

Fabrication of high current density Nb integrated circuits using a self-aligned junction anodization process

We have developed a self-aligned Nb/Al-AlO/sub x//Nb junction anodization process that allows outside junction contacts and relaxed contact alignment. In this process, the junction, rather than the junction contact, becomes the minimum definable feature size. Junction size is limited only by the resolution of the lithography and etch tools, which is 0.65 /spl mu/m in our foundry. The self-aligned junction anodization process allows a significant increase in circuit speed due to the decrease in minimum junction size and increase in junction critical current density without investment in new fabrication tools. This process requires only one additional, noncritical masking step and has no impact on existing design rules. We describe the fabrication and electrical characteristics of lightly anodized junctions and arrays at 8 kA/cm/sup 2/ and the development of new 5 /spl Omega//sq. MoN/sub x/ and 0.15 /spl Omega//sq. Mo/Al resistors. We also discuss the 300 GHz T flip-flop benchmark results from our new 8 kA/cm/sup 2/, 1.25 /spl mu/m Nb integrated circuit process and compare these results to other Nb processes.

A high density 4 kA/cm/sup 2/ Nb integrated circuit process

We have developed an improved 4 kA/cm/sup 2/ process technology that allows a significant increase in circuit speed and density. Improved photoresist and dry etch processes have reduced critical dimension (CD) variation and improved CD linearity to below 1 /spl mu/m. These improvements have enabled a substantial reduction in feature size and full utilization of existing photolithography and etch tools. We have demonstrated mire pitch of 2.0 /spl mu/m with less than 0.1 /spl mu/m CD loss. Minimum junction diameter and contact are 1.75 /spl mu/m and 1.0 /spl mu/m, respectively. Junctions, fabricated using a new barrier oxidation method with improved pressure control, have excellent I-V characteristics and array I/sub c/ nonuniformity less than 1.6% (1/spl sigma/). We have demonstrated a 200 GHz, 12-stage divider circuit that is the fastest complex digital superconductor integrated circuit fabricated to date. With the present process tools, defects are the limiting factor to further increases in circuit density and yield. In this paper, we discuss process improvements, electrical performance, defect reduction, and circuit performance.

Manufacturability of superconductor electronics for a petaflops-scale computer

Ultra-low power and ultra-high speed single-flux-quantum electronics is an enabling near-term technology solution for petaflops-scale computers. The proposed Hybrid Technology Multi-threaded (HTMT) petaflops computer architecture includes computational modules operating at 100 GHz and an I/O throughput of 32 Petabits/s. Due to fundamental time-of-flight and power dissipation limitations of semiconductor ICs, superconductor ICs at an integration level of 100 k gates/cm/sup 2/ are proposed for the HTMT computation modules. In this paper, we discuss the manufacturability of superconductor-based computation modules, including the IC foundry process, packaging, and data link out of the cryopackage. We focus on the critical technical challenges that exist in each of these areas and present a technology roadmap to achieve the HTMT requirements.

All refractory NbN integrated circuit process

The authors describe the fabrication and electrical performance of an eight mask step, 2.5- mu m*2.5- mu m minimum junction size, all refractory NbN integrated circuit process. NbN/MgO/NbN trilayers sputtered in situ are patterned by reactive ion etching to form Josephson tunnel junctions. A two-level dielectric process has been developed to ensure low defect densities. Sputtered molybdenum films form a resistor layer. NbN wire J/sub c/ enhancement and improved step coverage have been achieved. This process has been used to successfully fabricate SQUID amplifier circuits, digital modified variable threshold logic circuits, arrays of 256 SQUIDs, SFQ counters, and 4000 junction strings. NbN logic circuit operation above 10 K was demonstrated.<<ETX>>

Superconductive multi-chip module process for high speed digital applications

We report on the development of a superconducting multi-chip module (MCM) process for high speed digital packaging applications, which allows superconducting microstrip connections of superconducting chips with impedances up to 50 /spl Omega/. The MCM process uses a low temperature polymer, benzocyclobutene (BCB) dielectric, which has excellent planarization properties (>90%). The six mask MCM process uses three Nb wire layers, two BCB layers, and Ti/Pd/Au for the pad metallization. To maximize yield of 32 mm square MCM die, we optimized Nb deposition and BCB curing parameters to minimize stress-induced failures and reduce defect density. Current-carrying capabilities of signal lines and vias (5 /spl mu/m minimum design rule) are in excess of 20 mA//spl mu/m linewidth. We discuss successful packaging of superconducting chips, demonstrating error-free operation up to 5 Gbit/s, and other process improvements, such as the use of NbN wiring for 10 K operation.

Differential SFQ transmission using either inductive or capacitive coupling

The bias current requirement for RSFQ circuits is about an ampere per thousand gates. High current increases the thermal load of cables into the cryostat, produces undesirable currents and fields on-chip, and makes efficient power supply difficult. Series-biasing has been proposed, whereby the circuit is divided into blocks powered in series. This requires floating ground planes for each block, and differential signal propagation across ground plane boundaries where the blocks communicate. We have demonstrated transmission of pseudo-random data across a differential link using two distinct approaches, based on magnetic and capacitive coupling. For each circuit, we have measured data rates up to 30 Gb/s and bit error rates down to 10/sup -10/. Bit error rates extrapolate to lower values. Inductive coupling was implemented in TRWs 4 kA/cm/sup 2/ Nb process, capacitive coupling in TRWs 8 kA/cm/sup 2/ process.

LTS Josephson junction critical current uniformities for LSI applications

Manufacturing yields of large scale superconducting circuits depend strongly on the uniformity of junction critical currents. We report on junction manufacturing tolerances based on extensive measurements of Nb- and NbN-based junction arrays and individual junctions. Transient waveforms induced by switching of a single junction have sufficient amplitude to switch other junctions in a series array. We have measured the effect of sympathetic switching and developed damping structures to dissipate switching transients. Comparisons of critical current distributions measured on individual junctions with critical current distributions determined from series junction arrays are presented. In addition, the validity of using series arrays of large numbers of junctions to assess the critical current uniformity is discussed.<<ETX>>

Next generation Nb superconductor integrated circuit process

We have developed our next generation Nb integrated circuit process which offers higher performance, particularly for SFQ-type logic, and increased density compared to our present 2000 A/cm/sup 2/ foundry process. The new process is based on our existing Nb foundry process, but has been optimized to utilize more of the sub-micron alignment and exposure capabilities of our optical lithography tools. Minimum linepitch and junction size have been reduced to 2.5 /spl mu/m (from 4 /spl mu/m) and 1.75 /spl mu/m (from 2.5 /spl mu/m), respectively, and J/sub c/ has been increased to 4000 A/cm/sup 2/. These goals have been achieved by an overall reduction in layer thicknesses, implementation of SF/sub 6/ dry etch for metal line definition, and optimization of the photolithography process. The new process offers lower inductance wiring and substantially lower parasitic circuit inductances compared with the existing Nb foundry process. In this paper, we discuss these improvements and report parametric test data for devices fabricated in this process.