M. A. Pawlak

Work function of Ni silicide phases on HfSiON and SiO/sub 2/: NiSi, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/, and Ni/sub 3/Si fully silicided gates

A complete determination of the effective work functions (WF) of NiSi, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/ and Ni/sub 3/Si on HfSiON and on SiO/sub 2/ is presented. Conditions for formation of fully silicided (FUSI) gates for NiSi/sub 2/, NiSi, Ni/sub 3/Si/sub 2/, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/ and Ni/sub 3/Si crystalline phases were identified. A double thickness series (HfSiON/SiO/sub 2/) was used to extract WF on HfSiON accounting for charge effects. A strong effect on WF of Ni content is observed for HfSiON, with higher WF for the Ni-rich silicides suggesting unpinning of the Fermi level. A mild dependence is observed for SiO/sub 2/. While all Ni-rich silicides have adequate WF for pMOS applications, Ni/sub 2/Si is most attractive due to its low formation temperature, lower volume expansion and ease of integration. Similar threshold voltages (-0.3 V) were obtained on Ni/sub 2/Si and Ni/sub 31/Si/sub 12/ FUSI HfSiON pMOSFETS.

Scalability of Ni FUSI gate processes: phase and Vt control to 30 nm gate lengths

We demonstrate for the first time the scalability of NiSi and Ni/sub 3/Si FUSI gate processes down to 30 nm gate lengths, with linewidth independent phase and V/sub t/ control. We show that 1-step FUSI is inadequate for NiSi FUSI gates, because it results in incomplete silicidation at low thermal budgets or in a linewidth dependent Ni silicide phase - inducing V/sub t/ shifts - at higher thermal budgets. We show that V/sub t/ and WF shifts are larger on high-K (HfO/sub 2/ (250 mV) or HfSiON (330mV)) than on SiON (110mV) and report Fermi level unpinning for Ni-rich FUSI on high-K. In contrast, we demonstrate the scalability of Ni/sub 3/Si FUSI, with no phase control issues, and report HfSiON Ni/sub 3/Si FUSI PMOS devices with V/sub t/= -0.33 V. Lastly, we show that, for NiSi, phase control down to narrow gate lengths can be obtained with a 2-step FUSI process.

CMOS Integration of Dual Work Function Phase-Controlled Ni Fully Silicided Gates (NMOS:NiSi, PMOS:

The CMOS integration of dual work function (WF) phase-controlled Ni fully silicided (FUSI) gates on HfSiON was investigated. For the first time, the integration of NiSi FUSI gates on n-channel MOS (NMOS) and Ni₃₁Si₁₂ FUSI gates on p-channel MOS (PMOS) with good V_t control to short gate lengths (L_G=50 nm, linear V_t of 0.49 V for NMOS, and -0.37 V for PMOS) is demonstrated. A poly-Si etch-back step was used to reduce the poly-Si height on PMOS devices, allowing for the linewidth-independent formation of NiSi on NMOS and Ni-rich silicides on PMOS with a two-step rapid thermal processing (RTP) silicidation process. The process space for the scalable formation of NiSi on NMOS and Ni₂Si or Ni₃₁Si₁₂ on PMOS devices was investigated. It was found that within the process window for linewidth-independent NiSi FUSI formation on 100-nm poly-Si NMOS devices, it is possible to control the silicide formation on PMOS devices by adjusting the poly-Si etch-back and RTP1 conditions to obtain either Ni₂Si or Ni₃₁Si₁₂ FUSI gates. A reduction in the PMOS threshold voltage of 90 mV and improved device performance (18% I_on improvement at I_off=100 nA/mum) was obtained for Ni ₃₁Si₁₂ compared to Ni₂Si FUSI gates, as well as a V_t reduction of 350 mV when compared to a single WF flow using NiSi FUSI gates on PMOS

\hbox{Ni}_{2}\hbox{Si}

The scalability of Ni fully silicided (FUSI) gate processes to short gate lengths was studied for NiSi, Ni₂Si, and Ni₃₁Si₁₂. It is shown that the control of the deposited Ni-to-Si ratio is not effective for phase and V_t control at short gate lengths. A transition to Ni-richer phases at short gate lengths was found for nonoptimized NiSi and Ni₂Si processes with excessive thermal budgets, resulting in significant V_t shifts for devices on HfSiON consistent with the difference in work function among the Ni silicide phases. Linewidth-independent phase control with smooth V_t rolloff characteristics was demonstrated for NiSi, Ni₂Si, and Ni₃₁Si₁₂ FUSI gates by controlling the Ni-to-Si reacted ratio through optimization of the thermal budget of silicidation (prior to selective Ni removal). Phase characterization over a wide temperature range indicated that the process windows for scalable NiSi and Ni₂Si are less than or equal to 25 degC, whereas a single-phase Ni₃₁Si₁₂ is obtained over an ~200degC temperature range

, and

We report the lowest leakage achieved to date in sub-0.5 nm EOT MIM capacitors compatible with DRAM flows, showing for the first time a path enabling scalability to the 3X nm node. A novel stack engineering consisting of: 1) novel controlled ultrathin Ru oxidation process, 2) TiO<inf>x</inf> interface layer, is used for the first time to achieve record low Jg-EOT in MIM capacitors using ALD Sr-rich STO high-k dielectric and thin Ru bottom electrode. Record low Jg of 10⁻⁶ A/cm² (10⁻⁸ A/cm²) is achieved for EOT of 0.4 nm (0.5 nm) at 0.8 V. Our data is compared favorably (> 100× Jg reduction at 0.4 nm) to previous best values in literature for MIMcaps with ALD dielectrics.

\hbox{Ni}_{31}\hbox{Si}_{12}

Low Vt Ni fully silicided (FUSI) devices are demonstrated making use of Al implantation for pMOS and Yb or Yb+P implantation for nMOS combined with Ni-silicide phase engineering. When Yb(+P) and Al implantation are followed by a high temperature anneal, significant segregation of Yb or Al toward the Ni-FUSI/SiON interface is observed and large Vt shifts of 450 mV (330 mV) and 200 mV are obtained for nMOS NiSi FUSI/SiON devices and pMOS Ni-rich FUSI/SiON devices, respectively, as compared to the undoped reference devices. The Vt shifts are preserved down to the shortest gate lengths. For both Al and Yb, the Vt shifts are explained by the dopants reacting with and modifying the dielectric. Thus, the low Vt dual implantation approach proposed achieves a low-cost dual dielectric implementation without the need of dual deposition of dielectrics or capping layers. In the case of Yb implantation followed by a high temperature anneal, a significant reduction in the inversion dielectric thickness is observed, indicating that the reaction between Yb and SiON results in the formation of a high-k dielectric. The Yb diffusion and reaction at the interface can be engineered using a P coimplant.

) on HfSiON

The narrow line behaviour observed for Co-silicide and Ni-silicide is investigated. The thermal degradation of Ni-silicide, morphological degradation as well as phase instability, is discussed. It is demonstrated that the thermal stability of Ni-silicide can be improved by alloying with Pt or Ta. The formation of Ni-silicide contacts on SiGe substrates is investigated. The stress induced by the silicide itself is studied by finite element simulations and verified with convergent beam electron diffraction analysis. Finally, the use of Ni-silicide as a metal gate is discussed.