M. Arienzo

Low‐temperature silicon cleaning via hydrogen passivation and conditions for epitaxy

In low‐temperature epitaxial Si deposition methods such as molecular beam epitaxy (MBE), pre‐epitaxial substrate preparation usually incorporates a high temperature (≳800 °C) step. Elimination of this step is essential to wider applicability of these epitaxial methods. We show that Si(100) wafers exposed to HF vapors in a laboratory ambience are bulk terminated and that such termination is stable in air for several tens of minutes, and in vacuum for several hours. It is possible to obtain good epitaxy, as determined by surface diffraction and transistor characteristics, provided epitaxy is commenced on these bulk‐terminated surfaces. We also give evidence that under certain conditions, bulk‐terminated surfaces are maintained in low‐temperature epitaxy using the method of ultrahigh vacuum chemical vapor deposition.

Diffusion of arsenic in bilayer polycrystalline silicon films

The diffusion of arsenic in polycrystalline silicon films is studied using a novel bilayer structure consisting of a polycrystalline silicon layer, in situ doped with arsenic, deposited on top of an undoped polycrystalline silicon layer. This technique avoids the complication of structural changes resulting from the ion implantation doping that has been employed in other investigations. The diffusivity is measured for the relatively low temperature range 700–850 °C and is described by the relation D=10 exp (−3.36/kT)cm2/s. The average deviation from this relation of the measurements from samples prepared in two different deposition systems is less than 20%. The values are about three orders of magnitude greater than the intrinsic diffusivity of arsenic in the silicon lattice. It is proposed that the diffusion takes place along grain boundaries and that certain background impurities in the grain boundaries are responsible for the large variation in the values that are reported in the literature.

Electron heating studies in silicon dioxide: Low fields and thick films

Novel metal‐oxide‐semiconductor structures with very large areas have been used together with the vacuum emission and carrier separation techniques to study electron heating down to low fields (≊1 MV/cm) and out to large oxide thicknesses (5200 A). At electric field magnitudes between 1.5 and 2.0 MV/cm, the threshold field for the onset of electron heating in silicon dioxide is observed. This onset is independent of oxide thickness and composition. Its value is consistent with all of the current theoretical calculations. At fields near threshold, a minimum average electronic energy of ≊1.0 eV is shown to be necessary to observe emission of the electrons into vacuum. Although the general trends in most of the data are approximately independent of oxide thickness out to 5200 A, certain thick oxide samples with higher water content and lower physical density do show deviations from stabilization at higher fields, particularly in the vacuum emission experiments. Also, the data tend to appear ‘‘noiser’’ as the...

SiGe alloys: growth, properties and applications

Abstract Due to advances in epitaxial techniques, the ability to deposit high-quality epitaxial silicon-germanium alloys at lower temperature, has opened up the applications of pseudomorphicSi1−xGex films in advanced bipolar transistors and in novel device structures. In this review paper, the various methods of growth of Si Ge alloys are discussed, including low-temperature epitaxy by ultra-high vacuum chemical vapor deposition (UHV/CVD) and molecular beam epitaxy (MBE). The morphology of growth and the stability of the deposited films are then presented. The major application of Si Ge alloys in integrated processes has been in the bipolar transistors area. The application of these alloys to the bandgap engineering of bipolar devices is discussed, including the most recent accomplishment of 75 GHzfT heterojunction bipolar transistors using Si Ge in the base.

SiGe heterojunctions: devices and applications

SiGe alloys have been successfully to a number of semiconductor devices, including bipolar heterojunction transistors, field effect transistors (FETs), tunneing and optoelectronic devices and structures. This review paper will first summarize the results obtained to-date in bipolar transistors, highlighting the design flexibility and the trade-offs offered by SiGe heterojunction technology an bandgap engineering, like junction field/capacitance control, liquid nitrogen operation and complementary processes. The leverage of this technology in high speed circuits will be discussed, including the record 75 GHz fT and 53 GHz fmax heterojunction bipolar transistors, and the achievement of sub-25 ps ECL ring oscillator delay. The applications of this technology to field effect transistors, to increase the channel mobility, to resonant tunneling structures, and to detectors and waveguides, to extend the use of silicon technology in optoelectronic are also reviewed.

Thin‐oxide dual‐electron‐injector annealing studies using conductivity and electron energy‐loss spectroscopy

A process to deposit in situ a dual electron injector structure (DEIS) with 5‐nm SiO2 between two Si‐rich SiO2 (SRO) layers of ∼20 nm each has been developed. The excess silicon, as evaluated by Auger spectroscopy and Rutherford backscattering, was of the order of 15%–17%, in agreement with previously reported values under similar deposition conditions. Thin cross‐sectioned samples of DEIS structures, both as‐deposited and annealed at 1000 °C with Ar in an oxygen and water‐moisture‐free atmosphere, were examined by spatially resolved energy‐loss spectroscopy (EELS) in a scanning transmission electron microscope. The analysis has shown that the excess silicon is present either as nanometer‐sized silicon islands or as submicroscopic silicon oxides of varying stoichiometry resulting from intermediate oxidation states (i.e., Si+3, Si+2, and Si+1). Additionally, the thermal anneal at 1000 °C did not appear to have any effect on silicon island size of the SRO layer in contact with the silicon substrate. This su...

Deposition of amorphous silicon using a tubular reactor with concentric‐electrode confinement

High‐quality, hydrogenated amorphous silicon (a‐Si:H) is deposited at room temperature by rf glow discharge at a high deposition rate using a tubular reactor with cylindrical symmetry (concentric‐electrode plasma‐enhanced chemical vapor deposition, CE‐PECVD). Using the novel CE‐PECVD design, room‐temperature deposition of a‐Si:H with growth rates up to 14 A s−1, low hydrogen concentration (≲10%), and the bonded hydrogen in the Si‐H monohydride configuration, is achieved for the first time using an rf glow‐discharge technique. The influence of the deposition parameters (silane flow rate, pressure, and power density) on the growth rate, optical band gap, and silicon‐hydrogen bonding configuration, is quantitatively predicted using a deposition mechanism based on the additive contribution of three growth precursors, SiH2, SiH3, and Si2H6, with decreasing sticking coefficients of 0.7, 0.1, and 0.001, respectively. The low hydrogen concentration is due to the enhanced ion bombardment resulting from the concent...

Electron avalanche injection on 10-nm dielectric films

Uniform electron avalanche injection has been successfully performed on 10‐nm SiO2 and on composite 8‐nm SiO2+4‐nm Si3N4 gate dielectrics. The films were grown on boron‐implanted substrates to obtain the optimum surface impurity concentration for uniform injection. The electrical properties indicated high‐quality and low‐defect density dielectrics with no deleterious effects introduced by the ion implantation. A voltage flat‐band Vfb shift and trap analysis were performed on both structures with and without post oxidation anneal, using metal or n‐polysilicon gate. The results obtained have confirmed the trends found in thicker oxides and pointed out the presence of deep water‐related centers. The composite structure, SiO2+Si3N4, showed high electron trapping due to two Coulombic centers normally invoked for Poole–Frenkel conduction in Si3N4. These centers are usually undetected by high‐field injection experiments.

Electrical characteristics of diodes fabricated in selective-epitaxial silicon wells

Abstract The selective epitaxial growth of silicon using SiO2 as a mask is investigated in this work. The silicon films were deposited using SiCl4, H2 and HCl in an atmospheric reactor at 1050°C. The structural aspects and electrical characteristics of Schottky barrier and diffused PN diodes fabricated in silicon islands formed with the selective-epitaxial deposition technique are reported. The influence of substrate resistivity and reactive ion teching on the quality of the selective-epi is examined and found to have no effect on the electrical characteristics. Diodes fabricated inside selective-epitaxial silicon wells far from the edges of the wells have different characteristics than those that include the edges and these differences are discussed.

Effect of post‐oxidation anneal on ultrathin SiO2 gate oxides

Ultrathin silicon oxide films 5–6 nm thick have been grown in a double‐walled furnace and annealed in N2 and Ar at temperatures varying between 850 and 1100 °C. The breakdown field distribution obtained is very tight and centered above 11 MV/cm for as‐grown oxides at 850 °C. The oxides that received a post‐oxidation anneal (POA) at 1000 °C show a consistent improvement in breakdown field distribution and breakdown charge density as compared to the oxides annealed at lower temperatures. Furthermore, under high field current stress, oxides with a POA at 1000 °C show a positive voltage flatband Vfb shift, while oxides with POA at a temperature T<1000 °C show a negative Vfb shift. These results point out the efficacy of a high‐temperature POA of 5–6 nm oxides on breakdown strength and on the reduction of some defects responsible for the positive charge trapping.