Jau-Yi Wu

Recent Progress in Phase-Change Memory Technology

We survey progress in the PCM field over the past five years, ranging from large-scale PCM demonstrations to materials improvements for high-temperature retention and faster switching. Both materials and new cell designs that support lower-power switching are discussed, as well as higher reliability for long cycling endurance. Two paths towards higher density are discussed: through 3D integration by the combination of PCM and 3D-capable access devices, and through multiple bits per cell, by understanding and managing resistance drift caused by structural relaxation of the amorphous phase. We also briefly survey work in the nascent field of brain-inspired neuromorphic systems that use PCM to implement non-Von Neumann computing.

A high performance phase change memory with fast switching speed and high temperature retention by engineering the Ge x Sb y Te z phase change material

Phase change memory has long suffered from conflicting material properties between switching speed and thermal stability. This study explores the engineering of GeSbTe ternary alloys along an isoelectronic tie line and the Ge/Sb2Te3 tie line with the hope of finding a high performance material. Our efforts resulted in a new material that considerably outperforms the conventional GST-225. The switching speed is similar to undoped GST-225, with ∼ 30% lower reset current, and nearly 100°C higher Tx, thus much better thermal stability. The promising properties of this new material are demonstrated in a 128Mb chip and tested both at wafer level and as packaged dies. These devices showed 1E8 cycling endurance and withstood 190 °C testing.

A low power phase change memory using thermally confined TaN/TiN bottom electrode

Application of phase change memory (PCM) has been limited by the high power required to reset the device (changing from crystalline to amorphous state by melting the phase change material). Utilizing the poor thermal and electrical conductivity of TaN we have designed a simple structure that thermally insulates the bottom electrode and thus drastically reduces the heat loss. A 39nm bottom electrode with a TaN thermal barrier and 1.5nm of TiN conductor has demonstrated 30µA reset current, representing a 90% reduction. The benefit of thermal insulation is understood through electrothermal simulation, and the benefit is demonstrated in a 256Mb test chip. The low reset current also improves the reliability and excellent cycling endurance >1E9 is observed. This low power device is promising for expanding the application for PCM.

Understanding amorphous states of phase-change memory using Frenkel-Poole model

A method based on Frenkel-Poole emission is proposed to model the amorphous state (high resistance state) in mushroom-type phase-change memory devices. The model provides unique insights to probe the device after amorphizing (RESET) operation. Even when the resistance appears the same under different RESET conditions, our model suggests that both the amorphous region size and the defect states are different. With this powerful new tool, detailed changes inside the amorphous GST for MLC operation and retention tests are revealed.

Mechanisms of retention loss in Ge 2 Sb 2 Te 5 -based Phase-Change Memory

Data retention loss from the amorphous (RESET) state over time in Phase-Change Memory cells is associated with spontaneous crystallization. In this paper, the change in the threshold voltage (VT) of memory cells in the RESET state before and after heating is used as a probe into the nature of the retention loss mechanisms. Two mechanisms for the retention loss behavior are identified, responsible for the main distribution and the tail distribution, respectively. Experimental results suggest that (i) an optimized RESET operation produces a fully amorphized Ge2Sb2Te5 (aGST) active region, with no crystalline domains inside, (ii) cells in the tail distribution fail to retain their RESET state due to spontaneous generation of crystallization nuclei and grain growth, and (iii) cells in the main distribution fail due to grain growth from the amorphous/crystalline GST boundary, instead of nucleation within the active region.

Atomic-level engineering of phase change material for novel fast-switching and high-endurance PCM for storage class memory application

Storage class memory (SCM) does not need long data retention (since the data are refreshed regularly) but has very stringent requirements on read/write speed and cycling endurance. Even though phase change memory (PCM) is a leading candidate currently no phase change material can satisfy both speed and endurance requirements. This is because although GST-225 is a fast switching material it suffers large volume change when melting thus limited cycling endurance. Attempts to improve the endurance so far must sacrifice switching speed. This work explores new phase change material by atomic-level engineering the doping to GST. The resulting new phase-change material has demonstrated fast switching speed of 20 ns, long endurance of 1G cycles and low reset current of 150 μA in a 128 Mb test chip. Its data retention passed 20 years-55°C criteria with failure rate lower than 10ppm.

Investigation of maximum current sensing window for two-side operation, four-bit/cell MLC nitride-trapping nonvolatile flash memories

Localized charges in a nitride-trapping device provide two-bit/cell operations. Adding multilevel-cells (MLCs) to the physical bits produces a four-bit/cell device. However, it is difficult to get sufficient sensing windows for MLC operation because the left bit and right bit interfere with each other. This letter analyzes the effect of the second bit effect and investigates parameters affecting the sensing current window for physical four-bit/cell operations. The sensing window is found to increase with a higher reading bias, and also with a higher programmed V/sub t/. However, severe second bit effects set in at high V/sub t/, and decreased the sensing window again. An optimal sensing window is found at moderately high V/sub t/.

7.3 A resistance-drift compensation scheme to reduce MLC PCM raw BER by over 100× for storage-class memory applications

The large performance gap between traditional storage and the rest of the memory hierarchy calls for a storage class memory (SCM) to fill the need. Phase change memory (PCM) is an emerging memory candidate for SCM with the advantages of scalability, bit-alterability, non-volatility, and high program speed. Previous publications demonstrated high-density single-level-cell (SLC) PCMs using circuits and architectural techniques for expanding memory capacity, increasing bandwidth, and enabling embedded applications [1-4]. For PCM to be a true contender, a multi-level-cell (MLC) topology with at least a moderate data retention time is required. However, the resistance-drift (R-drift) effect causes cell resistance (RCELL) to increase with time, exceeding the ECC correction ability within hours of being programmed. Conventional R-drift mitigation approaches using reference-cell-based resistance tracking (RCRT) [5] and DRAM-like refresh (DR) [6] are feasible, but at the cost of compromising distinguished PCM traits: random write, low latency, and low power. This paper proposes a resistance drift compensation (RDC) scheme to mitigate against R-drift without such compromises, while minimizing the speed and power consumption penalties. The MLC-PCM fixed-threshold retention (FTR) raw-bit-error-rate (RBER) has been suppressed by over two orders of magnitude, reducing it below practical ECC capability limits.

A novel inspection and annealing procedure to rejuvenate phase change memory from cycling-induced degradations for storage class memory applications

A novel Cycle Alarm Point (CAP) inspection is proposed to monitor PCM cycling degradation. The degradation appears in two stages - (1) right shift of R-I during moderate cycling degradation, and (2) left shift of R-I when cycling damage is severe. We further propose an In-Situ-Self-Anneal (ISSA) procedure, such that once a CAP signal is detected, the annealing procedure is issued to rejuvenate the cells. We demonstrate, for the first time, PCM cycling degradation can be recovered repeatedly. This opens a new window to extend PCM endurance and reliability for storage class memory (SCM) applications.

A novel self-converging write scheme for 2-bits/cell phase change memory for Storage Class Memory (SCM) application

A new phase change material that provides fast SET speed, high cycling endurance, and large resistance window suitable for MLC SCM is investigated. Thorough understanding of the factors that affect the resistance distribution taught us to avoid operating near the melting temperature of the phase change material. By exploiting the self-converging property of low current SET operation we have designed a novel write scheme that provides fast and accurate MLC programming. High performance and high reliability 2-bits/cell MLC is demonstrated on a 512Mb test chip.