M.C. Poon

Single grain thin-film-transistor (TFT) with SOI CMOS performance formed by metal-induced-lateral-crystallization

Metal-induced-lateral-crystallization (MILC) followed by high temperature annealing has been used for the first time to form, large single grain silicon from amorphous silicon. Polysilicon with grain size ranging from ten to hundred of microns can be formed by this method. By individually crystallizing the active area of a TFT, the entire transistor can be formed on a single or a small number of silicon grains with good controllability, thus similar to SOI structure. Test devices with thin t/sub ox/=120 /spl Aring/ have been fabricated and the performance is verified to be comparable to SOI MOSFETs. The scaling property of the grain enhanced TFTs has also been studied. The minimization of the device dimension results in smaller probability for the channel region of a TFT to cover multiple grains, which leads to better device performance.

XPS study of the thermal instability of HfO2 prepared by Hf sputtering in oxygen with RTA

Hafnium oxide (HfO 2 ) gate dielectric film was prepared by Hf sputtering in oxygen, and the thermal instability of HfO 2 was investigated by rapid thermal annealing (RTA) in nitrogen. X-ray photoelectron spectroscopy study reveals that the HfO 2 film is thermally unstable at postmetallization annealing temperatures (>500°C). The HfO 2 film decomposes and some oxygen atoms are released upon the RTA in nitrogen. In addition, the current-voltage characteristics of the Al/HfO 2 /Si capacitor are also highly unstable at temperatures higher than 300 K. These observations suggest that although HfO 2 has a much higher dielectric constant, it may not be suitable for the gate dielectric application because the postdeposition thermal treatment deteriorates both the physical and the electrical properties of the HfO 2 film.

Interface bonding structure of hafnium oxide prepared by direct sputtering of hafnium in oxygen

The interface properties of the hafnium gate oxide films prepared by direct sputtering of hafnium in oxygen with rapid thermal annealing have been investigated in detail. X-ray photoelectron spectroscopy reveals that the interface silicate layer is a random mixture of Hf–O, Si–O, Hf–Si, and excess Hf and Si atoms. The contributions of these bonds to the composition of silicate layer are governed by the Si/Hf ratio. At low Si/Hf ratio ( 9) and close to the substrate, Hf–Si dominates and the high strain Hf–Si bonds govern the electrical properties of the interface. These results explain the observed high interface trap density at the HfO2/Si interface and the soft breakdown behavior which is different from the silicon oxide film.

Effect of oxygen content and thickness of sputtered RuOx electrodes on the ferroelectric and fatigue properties of sol–gel PZT thin films

Sol–gel PZT thin-film capacitors with reactive sputtered RuOx electrodes were fabricated. The ferroelectric and fatigue properties of the capacitors were investigated with various oxygen content in the electrodes and different electrode thickness. Our results show that increase in oxygen content in the electrodes would improve the fatigue properties of the capacitors and the remanent polarization shows a maximum at a 10% oxygen partial pressure. These fatigue results are consistent with the oxygen vacancy model. Considerable degradation in ferroelectric and fatigue properties of the capacitors was observed when the electrode thickness was below 230 nm. Oxygen deficiency in the thin electrodes was detected through AES measurement. We propose that the effect of electrode thickness is attributed to the oxygen diffusion in the bottom electrode layers.

Approximation of the length of velocity saturation region in MOSFET's

This work presents an accurate approximation of the length of velocity saturation region (LVSR) based on the calculation of one-dimensional (1-D) electric field distribution near the drain region of MOSFETs. Results show that for short-channel devices (<1 /spl mu/m), the LVSR values calculated with the new model are much smaller than the conventional approach. The new model agrees well with the MINIMOS simulation results. According to the simulation and theoretical results, the length of velocity saturation region increases gradually with the drain bias and channel length.

Electrical characterization of the hafnium oxide prepared by direct sputtering of Hf in oxygen with rapid thermal annealing

Abstract Electrical characterization of the hafnium oxide (HfO 2 ) gate dielectric films prepared by Hf sputtering in oxygen was conducted. By measuring the current–voltage ( I – V ) characteristics at temperature ranging from 300 to 500 K, several abnormalities in the I – V characteristics are recorded. For temperatures below 400 K, the current–voltage characteristics in high field region can be plotted with the Fowler–Nordheim law but a stronger temperature dependence was observed. Large flatband voltage shifts in the Al/HfO 2 /Si capacitor were observed. The capacitance–voltage characteristics and flatband shifts are found to depend strongly on the post-deposition annealing temperature and duration. To study the reliability against high electric field, constant voltage stressing on the samples was conducted. We found that the trap energy levels are shallow and the oxide traps can be readily filled and detrapped at a low bias voltage.

Dielectric breakdown characteristics and interface trapping of hafnium oxide films

The breakdown characteristics of hafnium gate oxide prepared by direct sputtering with rapid thermal annealing are investigated in detail. We found that several soft breakdowns take place before a hard breakdown. Area and stress-voltage effects of the time-dependent dielectric breakdown are also observed. Results suggest that that the soft and hard breakdowns should have different precursor defects. A two-layer model of is proposed to explain these observations.

Low temperature doping of poly-SiGe films with boron by co-sputtering

Abstract SiGe films were boron doped by co-sputtering from Si-Ge-B target. Crystallization of amorphous SiGe films and dopant activation were realized by furnace annealing at 550 and 570°C, temperatures which are suitable for processing on Corning glass 7059. The composition of boron doped films and their crystallization process were analyzed by Rutherford backscattering spectroscopy, X-ray photoelectron spectroscopy and X-ray diffraction. Electrical properties of the films were characterized in Van der Pauw structure and by spreading resistance. Boron concentration incorporated in the films was in the range of 2 to 10% and the activated carrier concentration was between 6×10 18 –6×10 20 cm −3 . Very low resistivity of SiGe boron doped films in the range of 3–5 mΩ cm was obtained. It was also found that increased boron concentration leads to retarded crystallization of SiGe films.

A SPICE model for thin-film transistors fabricated on grain-enhanced polysilicon film

A simulation program with integrated circuit emphasis (SPICE)-compatible thin-film transistor (TFT) model for TFTs formed on grain-enhanced polysilicon (poly-Si) film by metal-induced-unilateral crystallization (MIUC) is presented. Due to the regularity of grain structures resulting from the MIUC process, the GBs are organized into a manhattan grid. The specific grain boundary (GB) organization allows a physics-based model to be developed. The model is based on the popular BSIM3 submicron CMOS model framework, which captures most of the physical effects in both long channel and short channel down to the submicron dimension. The model has been verified by a large amount of experimental data and shown to be applicable over a wide range of TFT processes with the application of grain-enhancement techniques such as solid-phase crystallization (SPC) and MIUC.

A statistical model to predict the performance variation of polysilicon TFTs formed by grain-enhancement technology

A statistical model to predict grain boundary distribution in the channel of a polysilicon thin-film transistor (TFT) is proposed. The model is valid for arbitrary transistor size to grain size ratio, and is particularly useful to predict the grain boundary distribution of recrystallized large-grain polysilicon TFTs where the transistor size is comparable to the grain size and gives significant device-to-device variation. The model has been extensively verified by comparing it with statistical data obtained from TFTs fabricated using metal-induced-lateral-crystallization and regular solid-phase epitaxial techniques. Good agreements between the experimental results and model prediction are demonstrated.