C.F. Cheng

A SPICE model for thin-film transistors fabricated on grain-enhanced polysilicon film

A simulation program with integrated circuit emphasis (SPICE)-compatible thin-film transistor (TFT) model for TFTs formed on grain-enhanced polysilicon (poly-Si) film by metal-induced-unilateral crystallization (MIUC) is presented. Due to the regularity of grain structures resulting from the MIUC process, the GBs are organized into a manhattan grid. The specific grain boundary (GB) organization allows a physics-based model to be developed. The model is based on the popular BSIM3 submicron CMOS model framework, which captures most of the physical effects in both long channel and short channel down to the submicron dimension. The model has been verified by a large amount of experimental data and shown to be applicable over a wide range of TFT processes with the application of grain-enhancement techniques such as solid-phase crystallization (SPC) and MIUC.

Modeling of grain growth mechanism by nickel silicide reactive grain boundary effect in metal-induced-lateral-crystallization

The growth mechanism of metal-induced-lateral-crystallization (MILC) was studied and modeled. Based on the time evolution of the metal impurity in the amorphous silicon film being crystallized, a model has been developed to predict the growth rate and the final metal distribution in the crystallized polysilicon. The model prediction has been compared with experimental results and high prediction accuracy is demonstrated. Using the model, the effects of annealing temperature, annealing time and initial metal concentration on the final grain size and metal impurity distribution can be analyzed. As a result, the model can be used to optimize the grain growth conditions for fabricating high performance thin-film-transistors on the recrystallized polysilicon film.

A statistical model to predict the performance variation of polysilicon TFTs formed by grain-enhancement technology

A statistical model to predict grain boundary distribution in the channel of a polysilicon thin-film transistor (TFT) is proposed. The model is valid for arbitrary transistor size to grain size ratio, and is particularly useful to predict the grain boundary distribution of recrystallized large-grain polysilicon TFTs where the transistor size is comparable to the grain size and gives significant device-to-device variation. The model has been extensively verified by comparing it with statistical data obtained from TFTs fabricated using metal-induced-lateral-crystallization and regular solid-phase epitaxial techniques. Good agreements between the experimental results and model prediction are demonstrated.

Modeling of large-grain polysilicon formation under retardation effect of SPC

This paper details the study of the mechanism of large-grain polysilicon layer formations using metal-induced lateral crystallization (MILC). A model is proposed to predict the growth rate of MILC under the retardation effect of solid-phase crystallization (SPC) at different annealing conditions. The model has been extensively validated by experimental data. This paper will show that the SPC exists as a counter-effect to retard the MILC and degrade the superiority of the polysilicon layer. The model has been used to predict the MILC rate of large-grain polysilicon grown by a pulsed-annealing technique that suppresses the undesirable SPC effect. The model prediction agrees well with the experimental results.

Effects of dopants on the electrical behavior of grain boundary in metal-induced crystallized polysilicon film

The effects of doping on the electrical behavior of grain boundary in large grain polysilicon-on-insulator (LPSOI) film formed by metal-induced lateral crystallization (MILC) with nickel is studied. It is found that N-channel MOSFETs formed on LPSOI film exhibits larger leakage current and more susceptible to punchthrough compared with P-channel MOSFETs. Strong correlation between leakage current of the devices and the electrical property of a single longitudinal grain boundary is observed. Through careful process calibration and experimental characterization, the effects of dopant on nickel atom diffusion and final transistor characteristics are reported.

Modeling of metal-induced-lateral-crystallization mechanism for optimization of high performance thin-film-transistor fabrication

A model to predict metal-induced-lateral-crystallization (MILC) growth rate, polysilicon grain size and metal impurity distribution is proposed. The accuracy of the model has been validated by experimental results obtained from SIMS analysis. It is believed that the model gives important information for superior MILC device fabrication and development.

Large-grain polysilicon crystallization enhancement using pulsed RTA

Enhanced metal-induced lateral crystallization (MILC) using a pulsed rapid thermal annealing (PRTA) technique to form a large-grain polysilicon layer has been investigated. By applying high temperature for a short period of time, MILC is enhanced while the background solid phase crystallization is suppressed. Experimental results show that the PRTA method is capable of increasing the rate of directional crystallization and improving the crystal quality of the recrystallized polysilicon layer. The overall annealing time and total thermal budget to achieve similar grain size as in constant temperature annealing is also reduced.

The effect of nickel thickness in nickel-induced-lateral-crystallization of amorphous Si

Nickel-Induced-Lateral-Crystallization (NILC) is highly considered as a low temperature alternative method for Solid-Phase-Crystallization (SPC). It can be employed to fabricate high performance TFTs. In this paper, the effect of Ni thickness on NILC was studied. It was found that the performance of an NILC TFT was improved when a thicker nickel thin film was used in the NILC process.

Impact of transistor-to-grain size statistics on large-grain polysilicon TFT characteristics

A model based on grain-boundary distribution to predict the impact of transistor-to-grain size statistics on transistor performance variation is proposed and extensively verified by experimental data. Using the model, optimization of transistor dimension with respect to grain size to achieve high mobility and low transistor-to-transistor variation to enhance the yield can be performed.

The effect of amorphous Si thickness in metal induced lateral crystallization technology

Metal Induced Lateral Crystallization (MILC) was carried out for amorphous Si (a-Si) with different thickness. The effect of a-Si thickness on MILC process was studied. We found that longer MILC region was obtained when a thinner a-Si layer was used. Thin-film transistors (TFT) were fabricated on the MILC poly-Si with different thickness. It was found that the TFTs on the thin MILC poly-Si layer have better performance than those on the thick MILC poly-Si layer. The results show that a thin (1000 /spl Aring/) a-Si layer should be used for MILC TFT fabrication, in order to obtain better TFT performances.