Ming Qin

Super thin-film transistor with SOI CMOS performance formed by a novel grain enhancement method

High performance super TFTs with different channel widths and lengths, formed by a novel grain enhancement method, are reported. High temperature annealing has been utilized to enhance the polysilicon grain and improve the quality of silicon crystal after low temperature MILC treatment on amorphous silicon. With device scaling, it is possible to fabricate the entire transistor on a single grain, thus giving the performance of single crystal SOI MOSFET. The effects of grain boundaries on device performance have been studied, indicating the existence of extra leakage current paths caused by the grain boundaries traversing the channel, which induced subthreshold hump and early punchthrough of wide devices. The probability for the channel region of a TFT to cover multiple grains decreases significantly when the device is scaled down, resulting in better device performance and higher uniformity.

Single grain thin-film-transistor (TFT) with SOI CMOS performance formed by metal-induced-lateral-crystallization

Metal-induced-lateral-crystallization (MILC) followed by high temperature annealing has been used for the first time to form, large single grain silicon from amorphous silicon. Polysilicon with grain size ranging from ten to hundred of microns can be formed by this method. By individually crystallizing the active area of a TFT, the entire transistor can be formed on a single or a small number of silicon grains with good controllability, thus similar to SOI structure. Test devices with thin t/sub ox/=120 /spl Aring/ have been fabricated and the performance is verified to be comparable to SOI MOSFETs. The scaling property of the grain enhanced TFTs has also been studied. The minimization of the device dimension results in smaller probability for the channel region of a TFT to cover multiple grains, which leads to better device performance.

A study of nickel silicide film as a mechanical material

Abstract Nickel silicide films, as a mechanical material, are investigated in detail. The film is prepared by high vacuum evaporation and rapid thermal annealing (RTA). The structure of the film is investigated by X-ray photoelectron spectroscopy (XPS) and atomic force microscope (AFM). It is shown that the resistivity of the film depends on the sintering temperature and keeps almost constant at the temperature from 400°C to 700°C. The stress of the film formed on c-Si is also measured, and it is found that it varies from −4.19×10 8 to 6.23×10 8 dyn/cm 2 (1 dyn/cm 2 =0.1 N/m 2 ) as the formation temperature varies from 250 to 700°C. The Youngs modulus of the film is measured to be 132 GPa, which means that the film has good elasticity. Finally, low stress micron-size NiSi micro-bridges and cantilevers have been demonstrated on silicon and oxide substrates.

SOI formation from amorphous silicon by metal-induced-lateral-crystallization (MILC) and subsequent high temperature annealing

In current SOI technology, the formation of circuit elements requires the use of some special starting material like SIMOX, BESOI or Unibond wafers, which usually cannot be made in-house. As such, it leads to a divergence between SOI technology and bulk technology, and there are debates on justification on the initial material cost. TFTs formed in polysilicon have similar structures to SOI, and have been used as the load element in SRAM. Comparing TFT and SOI transistors, the TFT is easier to fabricate in term of starting material and compatibility with bulk processes. However, its performance is usually very poor for high performance circuits. The TFT structure consists of a large number of small size crystallized silicon grains. It is desirable to have a very large grain size so that a single transistor can lie entirely on a single grain. In this case, the TFT becomes an SOI MOSFET. Metal-induced-lateral-crystallization (MILC) has been used to enlarge the polysilicon TFT grain size. However, due to the limitation in low temperature formation, the grain size is still not desirable. With the use of high temperature annealing at a temperature above 900/spl deg/C after MILC, we found that much larger crystals of the order of 10 /spl mu/m can be formed. For the advanced technology which comes with device scaling, it is possible to individually recrystallize the active region of each transistor, giving TFTs (as formed) with SOI MOSFET performance.

TFT fabrication on MILC polysilicon film with pulsed rapid thermal annealing

Thin film transistors have been fabricated on the polysilicon from the process of metal induced lateral crystallization and pulsed rapid thermal annealing. The result shows that process of 10 cycles of 1 second at 800/spl deg/C thermal pulse annealing has enhanced the grain sizes and the transistors fabricated have improvement which almost doubled the performance of those without the rapid thermal annealing. This method has high potential for use in the fabrication of thin film transistors on low temperature glass substrate and application in solar cell and LCD.

Effects of grain boundaries on TFTs formed by high-temperature MILC

The effects of grain boundaries on the performance of super TFTs formed by MILC are studied. The existence of grain boundaries in the channel region will cause subthreshold hump, early punchthrough or device degradation, depending on the direction of the grain boundaries. The probability for the channel region of a TFT to cover multiple grains decrease significantly when the device is scaled down, thus resulting in better device performance and higher uniformity. A novel method to measure the grain dimension by using boundaries oxide as a etching mask has also been developed.