M. Copel

Structure and stability of ultrathin zirconium oxide layers on Si(001)

We have examined the structure of ultrathin ZrO2 layers on Si(001) using medium energy ion scattering and cross-sectional transmission electron microscopy. Films can be deposited on SiO2 layers with highly abrupt interfaces by atomic layer deposition. On HF stripped Si(001), nucleation was inhibited, resulting in poorer film morphology. ZrO2 showed remarkable stability against silicate formation, with no intermixing even after high temperature oxidation. The oxide is vulnerable to high temperature vacuum annealing, with silicidation occurring at temperatures above 900 °C.

High-mobility ultrathin semiconducting films prepared by spin coating.

The ability to deposit and tailor reliable semiconducting films (with a particular recent emphasis on ultrathin systems) is indispensable for contemporary solid-state electronics. The search for thin-film semiconductors that provide simultaneously high carrier mobility and convenient solution-based deposition is also an important research direction, with the resulting expectations of new technologies (such as flexible or wearable computers, large-area high-resolution displays and electronic paper) and lower-cost device fabrication. Here we demonstrate a technique for spin coating ultrathin (∼50 Å), crystalline and continuous metal chalcogenide films, based on the low-temperature decomposition of highly soluble hydrazinium precursors. We fabricate thin-film field-effect transistors (TFTs) based on semiconducting SnS2-xSex films, which exhibit n-type transport, large current densities (>105 A cm-2) and mobilities greater than 10 cm2 V-1 s-1—an order of magnitude higher than previously reported values for spin-coated semiconductors. The spin-coating technique is expected to be applicable to a range of metal chalcogenides, particularly those based on main group metals, as well as for the fabrication of a variety of thin-film-based devices (for example, solar cells, thermoelectrics and memory devices).

High-resolution depth profiling in ultrathin Al2O3 films on Si

A combination of two complementary depth profiling techniques with sub-nm depth resolution, nuclear resonance profiling and medium energy ion scattering, and cross-sectional high-resolution transmission electron microscopy were used to study compositional and microstructural aspects of ultrathin (sub-10 nm) Al2O3 films on silicon. All three techniques demonstrate uniform continuous films of stoichiometric Al2O3 with abrupt interfaces. These film properties lead to the ability of making metal-oxide semiconductor devices with Al2O3 gate dielectric with equivalent electrical thickness in the sub-2 nm range.

Formation of a stratified lanthanum silicate dielectric by reaction with Si(001)

We have characterized the structure and electrical properties of lanthanum silicate layers formed on Si(001) by reaction of lanthanum oxide with the substrate. Postoxidation of the deposited films results in the formation of a stacked dielectric with a lanthanum silicate layer atop an interfacial layer of SiO2. This structure combines the interfacial properties of SiO2 with the large permittivity of lanthanum silicate. Although the resulting film has leakage properties far superior to an equivalent thickness of SiO2, there is evidence of significant quantities of ionic charge that must be eliminated before use in electronic applications.

Ultrathin HfO 2 films grown on Silicon by atomic layer deposition for advanced gate dielectrics applications

We report on growth behavior, structure, thermal stability and electrical properties of ultrathin (<10 nm) hafnium oxide films deposited by atomic layer deposition using sequential exposures of HfCl4 and H2O at 300°C on a bare silicon surface or a thin thermally grown SiO2-based interlayer. Compared to good quality continuous films deposited on SiO2 surfaces, HfO2 deposited on HF-last treated Si surfaces show a non-uniform, island-like morphology and poor electrical properties due to poor nucleation on H-terminated Si. As-deposited films have a significant amorphous component and undergo crystallization to a monoclinic phase above ∼500°C. Crystallization behavior is found to be dependent on film thickness with higher crystallization temperatures for thinner films. HfO2 on an ultrathin SiO2 interlayer shows good electrical properties with gate leakage current reduced by a factor of 103 -104 with respect to conventional SiO2 gate dielectrics which justifies its consideration as a candidate for high-K dielectric for future CMOS devices.

Ultrathin high-K gate stacks for advanced CMOS devices

Reviews recent progress in and outlines the issues for high-K high-temperature (/spl sim/1000/spl deg/C) poly-Si CMOS processes and devices and also demonstrate possible solutions. Specifically, we discuss device characteristics such as gate leakage currents, flatband voltage shifts, charge trapping, channel mobility, as well as integration and processing aspects. Results on a variety of high-K candidates including HfO/sub 2/, Al/sub 2/O/sub 3/, HfO/sub 2//Al/sub 2/O/sub 3/, ZrO/sub 2/, silicates, and AlN/sub y/(O/sub x/) deposited on silicon by different deposition techniques are shown to illustrate the complex issues for high-K dielectric integration into current Si technology.

Robustness of ultrathin aluminum oxide dielectrics on Si(001)

The stability of Al2O3 films during thermal processing will help determine their usefulness as an alternative gate dielectric for advanced complementary metal-oxide-semiconductor devices. We used medium energy ion scattering and atomic force microscopy to examine the degradation of ultrathin Al2O3 layers under ultrahigh vacuum annealing and the effects of low-temperature oxidation. No degradation is observed at 900 °C, but voids appear at higher temperatures. Growth of interfacial SiO2 takes place during low-pressure oxidation at 600 °C, which may limit the capacitance of extremely thin structures.

High mobility p-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric

We report Ge p-channel MOSFETs with a thin gate stack of Ge oxynitride and LTO on bulk Ge substrate without a Si cap layer. Excellent device characteristics (IV and CV) are achieved with subthreshold slope 82mV/dec. /spl sim/40% hole mobility enhancement is obtained over the Si control with a thermal SiO/sub 2/ gate dielectric. To our knowledge, this is the first demonstration of Ge MOSFETs with less than 10nm thick gate dielectric and less than 100mV/dec subthreshold slope.

Hafnium oxide gate dielectrics on sulfur-passivated germanium

Sulfur passivation of Ge(100) is achieved using aqueous ammonium sulfide (NH4)2S(aq). The passivation layer is largely preserved after atomic layer deposition of the high-κ dielectric material HfO2 when sufficiently low growth temperatures (e.g., 220°C) are employed. Oxygen incorporation is moderate and results in an electrically passivating GeOS interface layer. The HfO2∕GeOS∕Ge gate stack exhibits lower fixed charge and interface state density than a more conventional HfO2∕GeON∕Ge gate stack fabricated via an ammonia gas treatment.

Growth temperature dependence of interfacial abruptness in Si/Ge heteroepitaxy studied by Raman spectroscopy and medium energy ion scattering

The influence of growth temperature on the interfacial abruptness of strained Ge layers, a few monolayers thick, embedded in Si has been studied using Raman spectroscopy to identify the presence of GeGe and GeSi bonds and medium energy ion scattering to characterize the spatial extent of the layers. Atomically sharp interfaces are observed for growth temperatures just above the crystalline to amorphous transition range, with pseudomorphic growth found for growth temperatures >∼250 °C. Asymmetric mixing of Ge into the Si capping layer occurs during growth at higher temperatures. Significantly less intermixing occurs on annealing after growth, pointing to the role of dynamical processes occurring at the growth front.