M.J. Bellido

SODS: a new CMOS differential-type structure

Differential-type structures to implement boolean functions find very interesting applications in self-timed circuits. A new structure of CMOS differential circuits is presented in this communication. This cell has been implemented on a standard 1.5 ¿m technology and has served to assess the structure and compare it with previously reported differential structures. Experimental laboratory results show improved timing and power performance, as well as gain in terms of transistor-count and area.

Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation

Opening.- The First Quartz Electronic Watch.- Arithmetics.- An Improved Power Macro-Model for Arithmetic Datapath Components.- Performance Comparison of VLSI Adders Using Logical Effort.- MDSP: A High-Performance Low-Power DSP Architecture.- Low-Level Modeling and Characterization.- Impact of Technology in Power-Grid-Induced Noise.- Exploiting Metal Layer Characteristics for Low-Power Routing.- Crosstalk Measurement Technique for CMOS ICs.- Instrumentation Set-up for Instruction Level Power Modeling.- Asynchronous and Adiabatic Techniques.- Low-Power Asynchronous A/D Conversion.- Optimal Two-Level Delay - Insensitive Implementation of Logic Functions.- Resonant Multistage Charging of Dominant Capacitances.- A New Methodology to Design Low-Power Asynchronous Circuits.- Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library.- CAD Tools and Algorithms.- Clocking and Clocked Storage Elements in Multi-GHz Environment.- Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment.- Transistor Level Synthesis Dedicated to Fast I.P. Prototyping.- Robust SAT-Based Search Algorithm for Leakage Power Reduction.- Timing.- PA-ZSA (Power-Aware Zero-Slack Algorithm): A Graph-Based Timing Analysis for Ultra-Low Power CMOS VLSI.- A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems.- Clock Distribution Network Optimization under Self-Heating and Timing Constraints.- A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches.- Gate-Level Modeling.- A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers.- Output Waveform Evaluation of Basic Pass Transistor Structure.- An Approach to Energy Consumption Modeling in RC Ladder Circuits.- Structure Independent Representation of Output Transition Time for CMOS Library.- Memory Optimization.- A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors.- Design and Realization of a Low Power Register File Using Energy Model.- Register File Energy Reduction by Operand Data Reuse.- Energy-Efficient Design of the Reorder Buffer.- High-Level Modeling and Design.- Trends in Ultralow-Voltage RAM Technology.- Offine Data Profiling Techniques to Enhance Memory Compression in Embedded Systems.- Performance and Power Comparative Study of Discrete Wavelet Transform on Programmable Processors.- Power Consumption Estimation of a C Program for Data-Intensive Applications.- Communications Modeling and Activity Reduction.- A Low Overhead Auto-Optimizing Bus Encoding Scheme for Low Power Data Transmission.- Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level.- Low-Power FSMs in FPGA: Encoding Alternatives.- Synthetic Generation of Events for Address-Event-Representation Communications.- Posters.- Reducing Energy Consumption via Low-Cost Value Prediction.- Dynamic Voltage Scheduling for Real Time Asynchronous Systems.- Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level.- Power Efficient Vector Quantization Design Using Pixel Truncation.- Minimizing Spurious Switching Activities in CMOS Circuits.- Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates.- Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines.- Selective Clock-Gating for Low Power/Low Noise Synchronous Counters.- Probabilistic Power Estimation for Digital Signal Processing Architectures.- Modeling of Propagation Delay of a First Order Circuit with a Ramp Input.- Characterization of Normal Propagation Delay for Delay Degradation Model (DDM).- Automated Design Methodology for CMOS Analog Circuit Blocks in Complex Systems.

A simple binary random number generator: new approaches for CMOS VLSI

Random number generators (RNGs) based upon metastable operation in a CMOS latch are presented. Some different techniques to force metastable operation and detect the final state are also reported. Prototypes have been integrated and sequences produced by these generators have passed standard tests, exhibiting good random behavior.<<ETX>>

Python as a hardware description language: A case study

Many people may see the development of software and hardware like different disciplines. However, there are great similarities between them that have been shown due to the appearance of extensions for general purpose programming languages for its use as hardware description languages. In this contribution, the approach proposed by the MyHDL package to use Python as an HDL is analyzed by making a comparative study. This study is based on the independent application of Verilog and Python based flows to the development of a real peripheral. The use of MyHDL has revealed to be a powerful and promising tool, not only because of the surprising results, but also because it opens new horizons towards the development of new techniques for modeling and verification, using the full power of one of the most versatile programming languages nowadays.

Digital Data Processing Peripheral Design for an Embedded Application based on the Microblaze Soft Core

In this paper we present a design of a peripheral for microblaze soft core processor as part of a R+D project carried out in cooperation with three different companies. The objective of the project consisted in the development of an embedded system with a SoC implemented on a FPGA custom-designed board. This work addresses the design of a digital data processing peripheral included as a part of the target SoC application, that process digital signals via the digital inputs on a proposed board. Peripheral functionality is configurable for each digital signal independently and is configured from the software running on the microblaze processor core.

Degradation Delay Model Extension to CMOS Gates

This contribution extends the Degradation Delay Model (DDM), previously developed for CMOS inverters, to simple logic gates. A gate-level approach is followed. At a first stage, all input collisions producing degradation are studied and classified. Then, an exhaustive model is proposed, which defines a set of parameters for each particular collision. This way, a full and accurate description of the degradation effect is obtained (compared to HSPICE) at the cost of storing a rather high number of parameters. To solve that, a simplified model is also proposed maintaining similar accuracy but with a reduced number of parameters and a simplified characterization process. Finally, the complexity of both models is compared.

Inertial and degradation delay model for CMOS logic gates

The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital simulation. The model combines the degradation delay model presented in previous papers with a new algorithm to handle the inertial effect, and is able to take account of the propagation and filtering of arbitrarily narrow pulses (glitches, etc.). The model clearly overcomes the limitations of conventional approaches.

Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits

This communication shows the influence of clocking schemes on the digital switching noise generation. It will be shown how the choice of a suited clocking scheme for the digital part reduces the switching noise, thus alleviating the problematic associated to limitations of performances in mixed-signal Analog/Digital Integrated Circuits. Simulation data of a pipelined XOR chain using both a single-phase and a two-phase clocking schemes, as well as of two n-bit counters with different clocking styles lead, as conclusions, to recommend multiple clock-phase and asynchronous styles for reducing switching noise.

Modular asynchronous arbiter insensitive to metastability

The purpose of this paper is to present a novel modular N-user asynchronous arbiter circuit which is insensitive to metastable operation (i.e., the new arbiter cannot fail because of metastability), operating asynchronously and incorporating a modular architecture. A 1.5 /spl mu/m CMOS prototype arbiter has been designed and tested. Laboratory tests demonstrate the arbiter operates correctly.

Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements

This contribution successfully accomplished the design and implementation of an advanced DSP circuit for direct measurements of electrical network parameters (RMS and real and reactive power) with application to network monitoring and quality assurance. The device is implemented on a mid-range Xilinx Spartan-3 family FPGA and includes an OPE interface so that it can be integrated as a standard peripheral of a microprocessor system like the MicroBlaze. Special attention has been paid to resources optimization and accuracy with simulated error below 1%.