Paulino Ruiz-de-Clavijo

Degradation Delay Model Extension to CMOS Gates

This contribution extends the Degradation Delay Model (DDM), previously developed for CMOS inverters, to simple logic gates. A gate-level approach is followed. At a first stage, all input collisions producing degradation are studied and classified. Then, an exhaustive model is proposed, which defines a set of parameters for each particular collision. This way, a full and accurate description of the degradation effect is obtained (compared to HSPICE) at the cost of storing a rather high number of parameters. To solve that, a simplified model is also proposed maintaining similar accuracy but with a reduced number of parameters and a simplified characterization process. Finally, the complexity of both models is compared.

Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements

This contribution successfully accomplished the design and implementation of an advanced DSP circuit for direct measurements of electrical network parameters (RMS and real and reactive power) with application to network monitoring and quality assurance. The device is implemented on a mid-range Xilinx Spartan-3 family FPGA and includes an OPE interface so that it can be integrated as a standard peripheral of a microprocessor system like the MicroBlaze. Special attention has been paid to resources optimization and accuracy with simulated error below 1%.

Design and implementation of a SNTP client on FPGA

This contribution presents the design and implementation of a SNTP client module suitable for IEC 61850 environments fully done in hardware. The module is able to provide synchronization and accurate time reference within a microsecond with respect to a SNTP server, in a extremely compact, cost-effective and low power device completely implemented in a low grade FPGA chip. Therefore it can be an ideal replacement to expensive computer-based solutions or dedicated GPS receivers in a wide range of industrial applications. This SNTP client is part of a common technological platform for implementing Remote Terminal Units (RTUs) under IEC 61850.

Characterization of Normal Propagation Delay for Delay Degradation Model (DDM)

In previous papers we have presented a very accurate model that handles the generation and propagation of glitches, which makes an important headway in logic timing simulation. This model is called Delay Degradation Model (DDM). Characterizing DDM completely also implies the characterization of the normal propagation delay. In this paper, we propose a simple heuristic model that includes its dependence on the output load and the input transition time. We have tested this model and found a mean deviation lower than 4%. Also, we present a characterization process for this model that is fully integrated into AUTODDM without affecting the total simulation time needed to characterize a standard cell.

Internode: internal node logic computational model

In this work, we present a computational behavioral model for logic gates called Internode (Internal Node Logic Computational Model) that considers the functionality of the gate as well as all the different internal states the gate can reach. This computational model can be used in logic-level tools and is valid for any dynamic behavioral model (delay models, power models, switching noise models, etc.). Also, we show a very efficient implementation of the model, in C language, for N-inputs SCMOS NOR/NAND gates. Finally, we demonstrate the functionality of the model showing three different examples of modeling: (a) a propagation delay model, (b) the degradation delay model (DDM), and (c) a simple power model.

Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation

Discrete microprocessor-based equipment is a typical synchronization system on the market which implements the most critical features of the synchronization protocols in hardware and the synchronization algorithms in software. In this paper, a new clock discipline algorithm for hardware implementation is presented, allowing for full hardware implementation of synchronization systems. Measurements on field-programmable gate array prototypes show a fast convergence time (below 10 s) and a high accuracy (1 μs ) for typical configuration parameters.

Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level

This contribution presents a method to obtain current estimations at the logic level. This method uses a simple current model and a current curve generation algorithm that is implemented as an attached module to a logic simulator under development called HALOTIS. The implementation is aimed at efficiency and overall estimations, making it suitable to switching noise evaluation and current peaks localisation. Simulation results and comparison to HSPICE confirm the usefulness and efficiency of the approach.

AUTODDM: automatic characterization tool for the delay degradation model

As delay models used in logic timing simulation become more and more complex, the problem of model parameter values extraction arise as an important issue, which it is necessary to face in order to achieve a practical implementation of the model. In this way, this paper describes the characterization process associated with the previously developed delay degradation model for CMOS logic gates (DDM) and the implementation of an automatic characterization tool that automates the process and allows easy and fast model parameter extraction.

Design of a FFT/IFFT module as an IP core suitable for embedded systems

In this work, we have laid the foundations that allow us to accomplish the implementation of a FFT/IFFT module as an IP core. The main objective is to design a configurable optimized core that can be integrated as a standard peripheral of a microprocessor system. Thus, three different methodologies have been compared: VHDL coding, System-level tools at RT level, and System-level tools at macroblock level; in order to propose a general methodology that facilitates the design process as well as allows designers to maintain total control over the module internal architecture.

Signal Sampling Based Transition Modeling for Digital Gates Characterization

Current characterization methods introduce an important error in the measurement process. In this paper, we present a novel method to drive the timing characterization of logic gates under variable input transition times. The method is based on sampling and scaling realistic transition waveforms and it is easy to implement and introduces negligible computational overhead in the characterization process. We show how models characterized using the proposed method may improve accuracy from 5% to 8%.