Antonio J. Acosta

SODS: a new CMOS differential-type structure

Differential-type structures to implement boolean functions find very interesting applications in self-timed circuits. A new structure of CMOS differential circuits is presented in this communication. This cell has been implemented on a standard 1.5 ¿m technology and has served to assess the structure and compare it with previously reported differential structures. Experimental laboratory results show improved timing and power performance, as well as gain in terms of transistor-count and area.

Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation

Opening.- The First Quartz Electronic Watch.- Arithmetics.- An Improved Power Macro-Model for Arithmetic Datapath Components.- Performance Comparison of VLSI Adders Using Logical Effort.- MDSP: A High-Performance Low-Power DSP Architecture.- Low-Level Modeling and Characterization.- Impact of Technology in Power-Grid-Induced Noise.- Exploiting Metal Layer Characteristics for Low-Power Routing.- Crosstalk Measurement Technique for CMOS ICs.- Instrumentation Set-up for Instruction Level Power Modeling.- Asynchronous and Adiabatic Techniques.- Low-Power Asynchronous A/D Conversion.- Optimal Two-Level Delay - Insensitive Implementation of Logic Functions.- Resonant Multistage Charging of Dominant Capacitances.- A New Methodology to Design Low-Power Asynchronous Circuits.- Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library.- CAD Tools and Algorithms.- Clocking and Clocked Storage Elements in Multi-GHz Environment.- Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment.- Transistor Level Synthesis Dedicated to Fast I.P. Prototyping.- Robust SAT-Based Search Algorithm for Leakage Power Reduction.- Timing.- PA-ZSA (Power-Aware Zero-Slack Algorithm): A Graph-Based Timing Analysis for Ultra-Low Power CMOS VLSI.- A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems.- Clock Distribution Network Optimization under Self-Heating and Timing Constraints.- A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches.- Gate-Level Modeling.- A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers.- Output Waveform Evaluation of Basic Pass Transistor Structure.- An Approach to Energy Consumption Modeling in RC Ladder Circuits.- Structure Independent Representation of Output Transition Time for CMOS Library.- Memory Optimization.- A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors.- Design and Realization of a Low Power Register File Using Energy Model.- Register File Energy Reduction by Operand Data Reuse.- Energy-Efficient Design of the Reorder Buffer.- High-Level Modeling and Design.- Trends in Ultralow-Voltage RAM Technology.- Offine Data Profiling Techniques to Enhance Memory Compression in Embedded Systems.- Performance and Power Comparative Study of Discrete Wavelet Transform on Programmable Processors.- Power Consumption Estimation of a C Program for Data-Intensive Applications.- Communications Modeling and Activity Reduction.- A Low Overhead Auto-Optimizing Bus Encoding Scheme for Low Power Data Transmission.- Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level.- Low-Power FSMs in FPGA: Encoding Alternatives.- Synthetic Generation of Events for Address-Event-Representation Communications.- Posters.- Reducing Energy Consumption via Low-Cost Value Prediction.- Dynamic Voltage Scheduling for Real Time Asynchronous Systems.- Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level.- Power Efficient Vector Quantization Design Using Pixel Truncation.- Minimizing Spurious Switching Activities in CMOS Circuits.- Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates.- Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines.- Selective Clock-Gating for Low Power/Low Noise Synchronous Counters.- Probabilistic Power Estimation for Digital Signal Processing Architectures.- Modeling of Propagation Delay of a First Order Circuit with a Ramp Input.- Characterization of Normal Propagation Delay for Delay Degradation Model (DDM).- Automated Design Methodology for CMOS Analog Circuit Blocks in Complex Systems.

A simple binary random number generator: new approaches for CMOS VLSI

Random number generators (RNGs) based upon metastable operation in a CMOS latch are presented. Some different techniques to force metastable operation and detect the final state are also reported. Prototypes have been integrated and sequences produced by these generators have passed standard tests, exhibiting good random behavior.<<ETX>>

A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits

Cryptocircuits can be attacked by third parties using differential power analysis (DPA), which uses power consumption dependence on data being processed to reveal critical information. To protect security devices against this issue, differential logic styles with (almost) constant power dissipation are widely used. However, to use such circuits effectively for secure applications it is necessary to eliminate any energy-secure flaw in security in the shape of memory effects that could leak information. This paper proposes a design methodology to improve pull-down logic configuration for secure differential gates by redistributing the charge stored in internal nodes and thus, removing memory effects that represent a significant threat to security. To evaluate the methodology, it was applied to the design of AND/NAND and XOR/XNOR gates in a 90 nm technology, adopting the sense amplifier based logic (SABL) style for the pull-up network. The proposed solutions leak less information than typical SABL gates, increasing security by at least two orders of magnitude and with negligible performance degradation. A simulation-based DPA attack on the Sbox9 cryptographic module used in the Kasumi algorithm, implemented with complementary metal-oxide-semiconductor, SABL and proposed gates, was performed. The results obtained illustrate that the number of measurements needed to disclose the key increased by much more than one order of magnitude when using our proposal. This paper also discusses how the effectivenness of DPA attacks is influenced by operating temperature and details how to insure energy-secure operations in the new proposals.

Optimization of clock-gating structures for low-leakage high-performance applications

Clock Gating (CG) is a well known technique to reduce dynamic power consumption by stopping the clock to avoid unnecessary transitions in synchronous circuits. The abilities of different CG-styles to save power at a flip-flop level, depending on the input activity, are analysed in this paper. Also, since conventional CG techniques usually do not take into account leakage power, some optimization procedures and guidelines are presented for leakage reduction. Focusing on those structures that do not need a latch to remove undesired transitions in gated clock, a leakage value of a fourth of the original one is achieved without degradation in timing performances.

Analysis of High-Performance Flip-Flops for Submicron Mixed-Signal Applications

This paper presents a detailed analysis of high-performance edge-triggered memory elements for deep submicron mixed-signal applications. The variations of the main parameters (power, delay, peak of supply current) with supply voltage, as well as timing restrictions have been studied. Especial emphasis has been given to switching-noise generation, an aspect of important concern in mixed-signal applications. We have analyzed the sources of switching noise, noticing that, the less noisy flip-flops are those based on differential structures.

VHDL-based behavioural description of pipeline ADCs

This paper proposes a behavioural model for digitally corrected/calibrated pipeline A/D converters (ADCs) based on standard VHDL. We will show how VHDL-based analog modelling can be efficiently used to simulate and verify the functionality of these mixed-signal systems where significant interaction exists between analog and digital parts. The main motivation for describing the behavioural model (analog and digital) directly in standard VHDL is to make possible the synthesis and fault simulation of the digital part using standard digital tools. Results from simulations carried out using QuickHDL in Mentor-Graphics prove the feasibility of the approach and are in agreement with those obtained experimentally from a Silicon prototype.

A VHDL-based methodology for the design and verification of pipeline A/D converters

This paper proposes a methodology for designing sampled-data mixed-signal circuits by using VHDL-based behavioural descriptions. The goal is using a VHDL description of both the analog and the digital part, to simulate and verify the entire mixed-signal system, as well as to facilitate the synthesis and fault simulation of the digital part. As an example of the proposed methodology, a digitally corrected/calibrated pipeline A/D converter (ADC) has been designed. Among other aspects of general interest, we show how analog dynamic effects are incorporated in order to obtain accurate high level simulations. Results from simulations carried out using QuickHDL in MentorGraphics prove the feasibility of the approach and are in agreement with those obtained experimentally from a silicon prototype.

Degradation Delay Model Extension to CMOS Gates

This contribution extends the Degradation Delay Model (DDM), previously developed for CMOS inverters, to simple logic gates. A gate-level approach is followed. At a first stage, all input collisions producing degradation are studied and classified. Then, an exhaustive model is proposed, which defines a set of parameters for each particular collision. This way, a full and accurate description of the degradation effect is obtained (compared to HSPICE) at the cost of storing a rather high number of parameters. To solve that, a simplified model is also proposed maintaining similar accuracy but with a reduced number of parameters and a simplified characterization process. Finally, the complexity of both models is compared.

Inertial and degradation delay model for CMOS logic gates

The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital simulation. The model combines the degradation delay model presented in previous papers with a new algorithm to handle the inertial effect, and is able to take account of the propagation and filtering of arbitrarily narrow pulses (glitches, etc.). The model clearly overcomes the limitations of conventional approaches.