M. Valencia

SODS: a new CMOS differential-type structure

Differential-type structures to implement boolean functions find very interesting applications in self-timed circuits. A new structure of CMOS differential circuits is presented in this communication. This cell has been implemented on a standard 1.5 ¿m technology and has served to assess the structure and compare it with previously reported differential structures. Experimental laboratory results show improved timing and power performance, as well as gain in terms of transistor-count and area.

A simple binary random number generator: new approaches for CMOS VLSI

Random number generators (RNGs) based upon metastable operation in a CMOS latch are presented. Some different techniques to force metastable operation and detect the final state are also reported. Prototypes have been integrated and sequences produced by these generators have passed standard tests, exhibiting good random behavior.<<ETX>>

High radix implementation of Montgomery multipliers with CSA

Modular multiplication is the key operation in systems based on public key encryption, both for RSA and elliptic curve (ECC) systems. High performance hardware implementations of RSA and ECC systems use the Montgomery algorithm for modular multiplication, since it allows results to be obtained without performing the division operation. The aim of this article is to explore various modified structures of the Montgomery algorithm for high speed implementation. We present the implementation of a modified Montgomery algorithm with CSA and with different radix. In order to optimize the implementation regarding operation speed, we considered carry save adders structures and the Booth recoding scheme. The structure used in this paper simplifies the computation of the partial products avoiding the use of memories to store pre-calculated data for partial products which cannot be achieved by the shifting operation. The result shows that high-radix implementations are better for high speed applications.

Degradation Delay Model Extension to CMOS Gates

This contribution extends the Degradation Delay Model (DDM), previously developed for CMOS inverters, to simple logic gates. A gate-level approach is followed. At a first stage, all input collisions producing degradation are studied and classified. Then, an exhaustive model is proposed, which defines a set of parameters for each particular collision. This way, a full and accurate description of the degradation effect is obtained (compared to HSPICE) at the cost of storing a rather high number of parameters. To solve that, a simplified model is also proposed maintaining similar accuracy but with a reduced number of parameters and a simplified characterization process. Finally, the complexity of both models is compared.

Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits

This communication shows the influence of clocking schemes on the digital switching noise generation. It will be shown how the choice of a suited clocking scheme for the digital part reduces the switching noise, thus alleviating the problematic associated to limitations of performances in mixed-signal Analog/Digital Integrated Circuits. Simulation data of a pipelined XOR chain using both a single-phase and a two-phase clocking schemes, as well as of two n-bit counters with different clocking styles lead, as conclusions, to recommend multiple clock-phase and asynchronous styles for reducing switching noise.

Modular asynchronous arbiter insensitive to metastability

The purpose of this paper is to present a novel modular N-user asynchronous arbiter circuit which is insensitive to metastable operation (i.e., the new arbiter cannot fail because of metastability), operating asynchronously and incorporating a modular architecture. A 1.5 /spl mu/m CMOS prototype arbiter has been designed and tested. Laboratory tests demonstrate the arbiter operates correctly.

Metastable operation in RS flip-flops

A new model for representing the different types of behaviour exhibited by an RS flip-flop under metastable operation is presented. Although it reflects flip-flop transient operation, the new model handles logical variables instead of continuous time ones. The model is applied to flip-flops for both simultaneous input changes and runt pulses.

Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level

Accurate estimation of switching activity is very important in digital circuits. In this paper we present a comparison between the evaluation of the switching activity calculated using logic (Verilog) and electrical (HSPICE) simulators. We also study how the variation on the delay model (min, typ, max) and parasitic effects affect the number of transitions in the circuit. Results show a variable and significant overestimation of this measurement using logic simulators even when including postlayout effects. Furthermore, we show the contribution of glitches to the overall switching activity, giving that the treatment of glitches in conventional logic simulators is the main cause of switching activity overestimation.

HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model

This paper presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation algorithm based on different concepts for transitions and events. This new simulation algorithm is intended for including the inertial and degradation delay models. Simulation results are very similar to those obtained by electrical simulators, and show a higher accuracy compared to conventional delay models implemented in current logic simulators.

Analysis of Metastable Operation in a CMOS Dynamic D-Latch

Nowadays, metastability is becoming a serious problemin high-performance VLSI design, mainly due to the relatively-highprobability of error when a bistable circuit operates at highfrequencies. As far as we know, there is not any work publishedthat justifies and formally characterizes metastable behaviorin dynamic latches. With current technologies, dynamic latchesare widely used in high-performance VLSI circuits, mainly dueto their lower cost and higher operation speed than static latches.In this work, we demonstrate that dynamic memory cells presentan anomalous behavior referred to as metastable operation withcharacteristics similar to those of static latches. We performa suitable generalization of metastability to the dynamic case,applying it to a CMOS dynamic D-latch. A theoretical model willbe proposed, allowing the quantification of metastability, andit will be validated through electric simulation with HSPICE.After that, we have compared the metastable behavior of the dynamiclatch with its static counterpart, obtaining results about thecharacteristic parameters of metastability and the Mean TimeBetween Failures (MTBF) for both kinds of bistable circuits.These results have allowed us to conclude that, unlike metastabilitywindows in static latches, a clearly defined input interval existswhich produces an infinite resolution time. Regarding MTBF, thedynamic latch presents a very low MTBF value compared to thestatic latch. These results show that dynamic latches shouldnot be used in those circuits where the risk of asynchronismbetween clock and data signals is not negligible.