M.-J.E. Lee

Low-power area-efficient high-speed I/O circuit techniques

We present a 4-Gb/s I/O circuit that fits in 0.1-mm/sup 2/ of die area, dissipates 90 mW of power, and operates over 1 m of 7-mil 0.5-oz PCB trace in a 0.25-/spl mu/m CMOS technology. Swing reduction is used in an input-multiplexed transmitter to provide most of the speed advantage of an output-multiplexed architecture with significantly lower power and area. A delay-locked loop (DLL) using a supply-regulated inverter delay line gives very low jitter at a fraction of the power of a source-coupled delay line-based DLL. Receiver capacitive offset trimming decreases the minimum resolvable swing to 8 mV, greatly reducing the transmission energy without affecting the performance of the receive amplifier. These circuit techniques enable a high level of I/O integration to relieve the pin bandwidth bottleneck of modern VLSI chips.

A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips

A multiplying delay-locked loop (MDLL) for high-speed on-chip clock generation that overcomes the drawbacks of phase-locked loops (PLLs) such as jitter accumulation, high sensitivity to supply, and substrate noise is described. The MDLL design removes such drawbacks while maintaining the advantages of a PLL for multirate frequency multiplication. This design also uses a supply regulator and filter to further reduce on-chip jitter generation. The MDLL, implemented in 0.18-/spl mu/m CMOS technology, occupies a total active area of 0.05 mm/sup 2/ and has a speed range of 200 MHz to 2 GHz with selectable multiplication ratios of M=4, 5, 8, 10. The complete synthesizer, including the output clock buffers, dissipates 12 mW from a 1.8-V supply at 2.0 GHz. This MDLL architecture is used as a clock multiplier integrated on a single chip for a 72/spl times/72 STS-1 grooming switch and has a jitter of 1.73 ps (rms) and 13.1 ps (pk-pk).

Jitter transfer characteristics of delay-locked loops - theories and design techniques

This paper presents analyses and experimental results on the jitter transfer of delay-locked loops (DLLs). Through a z-domain model, we show that in a widely used DLL configuration, jitter peaking always exists and high-frequency jitter does not get attenuated as previous analyses suggest. This is true even in a first-order DLL and an overdamped second-order DLL. The amount of jitter peaking is shown to trade off with the tracking bandwidth and, therefore, the acquisition time. Techniques to reduce jitter amplification by loop filtering and phase filtering are discussed. Measurements from a prototype chip incorporating the discussed techniques confirm the prediction of the analytical model. In environments where the reference clock is noisy or where multiple timing circuits are cascaded, this jitter amplification effect should be carefully evaluated.

A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os

A 0.622-8-Gb/s clock and data recovery (CDR) circuit using injection locking for jitter suppression and phase interpolation in high-bandwidth system-on-chip solutions is described. A slave injection locked oscillator (SILO) is locked to a tracking aperture-multiplying DLL (TA-MDLL) via a coarse phase selection multiplexer (MUX). For the fine timing vernier, an interpolator DAC controls the injection strength of the MUX output into the SILO. This 1.2-V 0.13-/spl mu/m CMOS CDR consumes 33 mW at 8Gb/s. Die area including voltage regulator is 0.08 mm/sup 2/. Recovered clock jitter is 49 ps pk-pk at a 200-ppm bit-rate offset.

A 90 mW 4 Gb/s equalized I/O circuit with input offset cancellation

Recently-described CMOS serial links operate at multiple gigabits/s signaling rates over several meters of cable. However, these previous links require large amounts of power and chip area, making them unsuitable for applications requiring hundreds of I/Os per chip. The best previously-published power and area above 4 Gb/s in CMOS are 310 mW and 0.6 mm/sup 2/. Integration of a hundred of these I/Os would burn more than 30 W of power and consume 60 mm/sup 2/ of chip area. The 4 Gb/s transceiver described here dissipates only 90 mW and requires less than 0.1 mm/sup 2/ chip area. This transceiver achieves low-power and low area using an input-multiplexed transmitter architecture, a regulated CMOS inverter-based delay-locked loop (DLL), and receiver offset calibration.

High-performance electrical signaling

This paper reviews the technology of high-performance electrical signaling, presents the current state of the art, and projects future directions. We have demonstrated equalized electrical signaling between CMOS integrated circuits at data rates of 4Gb/s. As the factors that determine this signaling rate all scale with improving technology we expect the data rates of high-performance electrical signaling systems to improve on a Moores Law curve. The frequency-dependent attenuation of copper wires sets a bandwidth-distance squared (Bd/sup 2/) limit on the distance one can signal at a given data rate. Equalizing the channel cancels inter-symbol interference caused by this attenuation and greatly increases signaling distance. In the limit of perfect equalization, distance is ultimately limited by thermal noise in the receiver. At this limit, we calculate that a 4Gb/s system will be capable of operating over 100m of 24-gauge cable without repeaters.

An 84-mW 4-Gb/s clock and data recovery circuit for serial link applications

A 4 Gb/s serial link tracking clock and data recovery (CDR) circuit fabricated in 0.24 /spl mu/m CMOS technology dissipates 84 mW and occupies 0.3 mm/sup 2/. The input signal is 2/spl times/oversampled by 8 offset-cancelled receive amplifiers per receive clock cycle. The samples are processed by a phase controller to position the receive clocks at the center and the edge of the data eye using a semi-digital dual delay-locked loop (DLL). The quiet-supply p-p jitter of the receive clock is 39 ps with 0.33 ps/mV supply sensitivity. It allows for plesiochronous clocking with a frequency tolerance of /spl plusmn/400 ppm. The worst case phase resolution is <20 ps.

A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os

A 0.622-8 Gb/s CDR circuit using injection locking for jitter suppression and phase interpolation in high bandwidth SOC solutions is described. A slave injection locked oscillator (SILO) is locked to a tracking aperture-multiplying DLL (TA-MDLL) via a coarse phase selection MUX. For the fine timing vernier, an interpolator DAC controls the injection strength of the MUX output into the SILO. This 1.2 V 0.13 /spl mu/m CMOS CDR consumes 33 mW at 8 Gb/s. Die area, including voltage regulator, is 0.08 mm/sup 2/. Recovered clock jitter is 6.9 ps rms/49.3 ps peak-to-peak at a 200 ppm bitrate offset.

20Gb/s 0.13/spl mu/m CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer

A 20Gb/s transmitter is implemented in 0.13/spl mu/m CMOS technology. Eight 2.5Gb/s data streams are 4:1 multiplexed, sampled, and retimed into two 10Gb/s data streams. A final 20Gb/s 2:1 output multiplexer, clocked by complementary phases of an LC-VCO (voltage controlled oscillator) in a phase-locked loop, creates 20Gb/s data. The VCO is integrated with the output multiplexer, resonating the load and eliminating the need for clock buffers. Power, active die area, and jitter (RMS/pk-pk) are 165mW, 650/spl mu/m /spl times/ 350/spl mu/m, and 2.37ps/15ps, respectively.