Hiok-Tiaq Ng

A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips

A multiplying delay-locked loop (MDLL) for high-speed on-chip clock generation that overcomes the drawbacks of phase-locked loops (PLLs) such as jitter accumulation, high sensitivity to supply, and substrate noise is described. The MDLL design removes such drawbacks while maintaining the advantages of a PLL for multirate frequency multiplication. This design also uses a supply regulator and filter to further reduce on-chip jitter generation. The MDLL, implemented in 0.18-/spl mu/m CMOS technology, occupies a total active area of 0.05 mm/sup 2/ and has a speed range of 200 MHz to 2 GHz with selectable multiplication ratios of M=4, 5, 8, 10. The complete synthesizer, including the output clock buffers, dissipates 12 mW from a 1.8-V supply at 2.0 GHz. This MDLL architecture is used as a clock multiplier integrated on a single chip for a 72/spl times/72 STS-1 grooming switch and has a jitter of 1.73 ps (rms) and 13.1 ps (pk-pk).

Jitter transfer characteristics of delay-locked loops - theories and design techniques

This paper presents analyses and experimental results on the jitter transfer of delay-locked loops (DLLs). Through a z-domain model, we show that in a widely used DLL configuration, jitter peaking always exists and high-frequency jitter does not get attenuated as previous analyses suggest. This is true even in a first-order DLL and an overdamped second-order DLL. The amount of jitter peaking is shown to trade off with the tracking bandwidth and, therefore, the acquisition time. Techniques to reduce jitter amplification by loop filtering and phase filtering are discussed. Measurements from a prototype chip incorporating the discussed techniques confirm the prediction of the analytical model. In environments where the reference clock is noisy or where multiple timing circuits are cascaded, this jitter amplification effect should be carefully evaluated.

A multistage amplifier technique with embedded frequency compensation

A new multistage operational amplifier topology requires only N-2 embedded compensation networks for N gain stages. The compensation circuits do not load the output stage, and noninverting gain stages are not required as in previous multistage approaches. Consequently, high gain, wide bandwidth, fast slewing, and excellent power efficiency are achieved. A low-power resistance-capacitance compensation technique assures stability and fast settling over process, voltage, and temperature variations. Implemented in a 0.6-/spl mu/m n-well CMOS process, a single ended three-stage prototype dissipates 6.9 mW at 3.0 V with 102 dB gain, 47 MHz bandwidth, and 69 V//spl mu/s average slew rate with 40 pF load.

0.622-8.0 Gbps 150 mW serial IO macrocell with fully flexible preemphasis and equalization

This paper presents a 622 Mbps to 8 Gbps transceiver in standard 0.13 /spl mu/m CMOS technology. Each receiver and transmitter macrocell has its dedicated clock multiplication unit (CMU) and clock/data recovery unit (CDR), providing simultaneous multi-rate operation for multiple lanes on a chip. The transmitter and receiver front-end use direct 4:1 multiplex and 1:4 demultiplexing, using multiple-phase quarter-rate clocks. An automatic phase offset cancellation scheme is used to eliminate the phase mismatch of the multiple clock phases. Each transceiver occupies an active area of less than 0.4 mm/sup 2/ and consumes 150 mW at maximum speed.

A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os

A 0.622-8-Gb/s clock and data recovery (CDR) circuit using injection locking for jitter suppression and phase interpolation in high-bandwidth system-on-chip solutions is described. A slave injection locked oscillator (SILO) is locked to a tracking aperture-multiplying DLL (TA-MDLL) via a coarse phase selection multiplexer (MUX). For the fine timing vernier, an interpolator DAC controls the injection strength of the MUX output into the SILO. This 1.2-V 0.13-/spl mu/m CMOS CDR consumes 33 mW at 8Gb/s. Die area including voltage regulator is 0.08 mm/sup 2/. Recovered clock jitter is 49 ps pk-pk at a 200-ppm bit-rate offset.

A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os

A 0.622-8 Gb/s CDR circuit using injection locking for jitter suppression and phase interpolation in high bandwidth SOC solutions is described. A slave injection locked oscillator (SILO) is locked to a tracking aperture-multiplying DLL (TA-MDLL) via a coarse phase selection MUX. For the fine timing vernier, an interpolator DAC controls the injection strength of the MUX output into the SILO. This 1.2 V 0.13 /spl mu/m CMOS CDR consumes 33 mW at 8 Gb/s. Die area, including voltage regulator, is 0.08 mm/sup 2/. Recovered clock jitter is 6.9 ps rms/49.3 ps peak-to-peak at a 200 ppm bitrate offset.

A 48-Port FCC-Compliant 10GBASE-T Transmitter With Mixed-Mode Adaptive Echo Canceller

High density 48-port network switches demand very power-efficient, small form-factor physical layer transceivers which comply with the transmit PSD and return loss requirements, on the one hand, and meet the FCC Class-A specifications on the other hand, while achieving better than 10E-12 BER. The presented 10GBASE-T transmitter and hybrid utilize a current-mirroring amplifier with output rise-time control and high CMRR to perform a first-order linear and nonlinear echo cancellation while enabling the design of 48-port FCC compliant network switches. Experimental results over the 400-MHz bandwidth exhibit a worst case transmitter linearity of >;57 dBc as well as worst case post-hybrid fundamental and SFDR power of -18 and -70 dBc, respectively, across the 400-MHz frequency range of interest. The echo fundamental component is further attenuated to <; -60 dB in the analog domain by an adaptive mixed-mode echo canceller. Implemented in a 40-nm CMOS technology, the transmitter plus hybrid consumes 200 mW power and occupies 0.5 mm2.

A 16-port FCC-compliant 10GBase-T transmitter and hybrid with 76dBc SFDR up to 400MHz scalable to 48 ports

High-density 48-port network switches demand very power-efficient, small form-factor quad PHYs which comply with the IEEE 802.3an transmit PSD and return-loss requirements on the one hand and meet the FCC Class-A specifications on the other hand. We present a 10GBase-T transmitter and hybrid that uses a highly correlated current-mirroring amplifier with output rise time control and high CMRR to perform a first-order linear and non-linear echo cancellation while enabling the design of 48-port FCC compliant network switches. Experimental results over the 400MHz bandwidth exhibit a transmitter linearity of >;57dBc as well as a residual linear echo and distortion of -28dBc and 76dBc, respectively. Implemented in a 40nm CMOS technology, the transmitter plus hybrid consumes 200mW power and occupies 0.5mm2.