M. Karagounis

Counting and integrating readout for direct conversion X-ray imaging concept, realization and first prototype measurements

A novel signal processing concept for X-ray imaging with directly converting pixelated semiconductor sensors is presented. The novelty of this approach compared to existing concepts is the combination of charge integration and single photon counting in every single pixel. Simultaneous operation of both signal processing chains extends the dynamic range beyond the limits of the individual schemes and allows determination of the mean photon energy. Medical applications such as X-ray computed tomography can benefit from this additional spectral information through improved contrast and the ability to determine the hardening of the tube spectrum due to attenuation by the scanned object. A prototype chip in 0.35-micrometer technology was successfully tested. The pixel electronics are designed using a low-noise differential current mode logic and provide configurable feedback modes, leakage current compensation and various test circuits. This paper will discuss measurement results of the prototype structures and give details on the circuit design

Test beam results of 3D silicon pixel sensors for the ATLAS upgrade

Results on beam tests of 3D silicon pixel sensors aimed at the ATLAS Insertable B-Layer and High Luminosity LHC (HL-LHC) upgrades are presented. Measurements include charge collection, tracking efficiency and charge sharing between pixel cells, as a function of track incident angle, and were performed with and without a 1.6 T magnetic field oriented as the ATLAS inner detector solenoid field. Sensors were bump-bonded to the front-end chip currently used in the ATLAS pixel detector. Full 3D sensors, with electrodes penetrating through the entire wafer thickness and active edge, and double-sided 3D sensors with partially overlapping bias and read-out electrodes were tested and showed comparable performance.

An integrated Shunt-LDO regulator for serial powered systems

In this paper, a new type of regulator is proposed for integration in ASICs used in serially powered systems. In the serial powering scheme, modules are placed in series and fed by a constant current source to reduce the IR drop on the cables which increases powering efficiency. At the module level the needed supply voltages are generated redundantly out of the current supply by several parallel operating ASICs with integrated regulation circuitry. A Shunt-LDO regulator has been developed to allow robust and redundant regulator operation and the generation of different supply voltages by parallel placed devices. The Shunt-LDO regulator scheme combines the capability of Low Drop-Out regulators to generate a constant supply voltage with the feature of shunt regulators to assure a constant current flow through the device. The Shunt-LDO regulator has been developed for application in the framework of next generation hybrid pixel detectors used in high energy physics experiments. This circuit has been prototyped in a 130nm CMOS technology, capable of generating voltages in a range of 1.2-1.5V with a minimum drop out voltage of 200mV. The maximum shunt current is 500mA with a load regulation factor corresponding to an output impedance of 30mΩ.

Digital architecture and interface of the new ATLAS Pixel Front-End IC for upgraded LHC luminosity

A new pixel front-end integrated circuit is being developed in a 130 nm technology for use in the foreseen b-layer upgrade of the ATLAS pixel detector. Development of this chip is considered as an intermediate step towards super-LHC upgrade, and also allows having a smaller radius insertable pixel layer. The higher luminosity for which this chip is tuned implies a complete redefinition of the digital architecture logic with respect to the current ATLAS pixel front-end. The new digital architecture logic is not based on a transfer of all pixel hits to the periphery of the chip, but on local pixel logic, local pixel data storage, and a new mechanism to drain triggered hits from the double-column. An overview of the new chip will be given with particular emphasis on the new digital logic architecture and possible variations. The new interface needed to configure and operate the chip will also be described.

Digital architecture of the new ATLAS pixel chip FE-I4

With the high hit rate foreseen for the innermost layers at an upgraded LHC, the current ATLAS Front-End pixel chip FE-I3 [1] would start being inefficient. The main source of inefficiency comes from the copying mechanism of the pixel hits from the pixel array to the end of column buffers. A new ATLAS pixel chip FE-I4 is being developed in a 130 nm technology for use both in the framework of the Insertable B-Layer (IBL) project and for the outer layers of Super-LHC. FE-I4 is made of 80×336 pixels and features a reduced pixel size of 50×250 μm2. In the current design, a new digital architecture is introduced in which hit memories are distributed across the entire pixel array and the pixels organized in regions. In this paper, the digital architecture of FE-I4 is presented as well as the complete data flow.

AGIPD - The adaptive gain integrating pixel detector for the European XFEL development and status

The European XFEL [1] will provide fully coherent, 100 fs X-ray pulses, with up to 1012 photons at 12 keV. The high intensity per pulse will allow recording diffraction patterns of single particles or small crystals in a single shot. Consequently 2D-detectors have to cope with a large dynamic range: detection from single photon to > 104 photons/pixel in the same image. An additional challenge is the European XFEL machine: an Electron bunch train with 10 Hz repetition rate, consisting of up to 2,700 bunches with a 220 ns spacing. Recorded images have to be stored inside the pixel during the bunch trains and readout in between. To meet these requirements, the European XFEL has launched 3 detector development projects. The AGIPD project is a collaboration between DESY, PSI and the Universities of Bonn and Hamburg. The goal is a 1024 × 1024 pixel detector, with 200 µm pixel size and a central hole for the primary beam. The ASIC operates in charge integration mode: the output of each pixels preamplifier is proportional to the charge from the sensor generated by the X-rays. The input stage of the pixel cells uses dynamically adjustable gains. The output signal is stored in an analogue memory, which has to be a compromise between noise performance and the number of images. This is operated in random access mode, providing means to overwrite bad frames for optimal use of the 352 memory cells per pixel, which have to be readout and digitized in the 99.4ms bunch gap. The detector will be built of 8 × 2 fully depleted monolithic silicon sensors with a 8 × 2 array of CMOS readout chips bump-bonded to these. Several prototypes of the readout ASIC have been produced. The results presented originate from the 16 × 16 pixel matrices AGIPD 0.2, which was bump-bonded to a pixel sensor, and AGIPD 0.3, which includes the intended control algorithm and a fast differential interface to the off-chip world.

Development of a prototype module for a DEPFET pixel vertex detector for a linear collider

For operation at a linear collider the excellent noise performance of depleted field effect transistor (DEPFET) pixels allows building very thin detectors with high spatial resolution and low power consumption. However, high readout speeds of 50 MHz line rate and 20 kHz for the full detector must be reached. A prototype system is presented, using a new DEPFET pixel matrix (128 /spl times/ 64 pixels), fast steering chips (Switcher II) for row wise operation and a fast current based readout chip (CURO II). The sensors with small linear DEPFET pixels (22/spl times/36 /spl mu/m/sup 2/) are optimized for fast readout and high spatial resolution. Measurements show that the complete removal of the accumulated signal charge from the internal gate (complete clear), which is fundamental for the foreseen readout mode, is feasible. The current based readout chip CUROII, containing current memory cells, pedestal subtraction and on chip zero suppression for a triggerless operation has been fabricated and tested. First results of a full prototype system are presented.

A serial powering scheme for the ATLAS pixel detector at sLHC

Powering concepts, such as serial powering and DC-DC conversion, are in development for the silicon trackers at sLHC to achieve an efficient power distribution with a minimum volume of cables. This paper will describe the serial powering scheme developed for the upgraded ATLAS pixel detector, with focus on the scheme architecture and on the main components involved: the Shunt-LDO regulator and the protection scheme. Issues connected to system aspects will be discussed, and the advantages in terms of material reduction provided by the proposed serial powering scheme will be presented.

Digital Architecture and Interface of the New ATLAS Pixel Front-End IC for Upgraded LHC Luminosity

A new pixel Front-End Integrated Circuit is being developed in a 130nm technology for use in the foreseen b-layer upgrade of the ATLAS Pixel Detector. Development of this chip is considered as an intermediate step towards super-LHC upgrade, and also allows having a smaller radius insertable pixel layer. The higher luminosity for which this chip is tuned implies a complete redefinition of the digital architecture logic with respect to the current ATLAS pixel Front-End. The new digital architecture logic is not based on a transfer of all pixel hits to the End-of-Column, but on local pixel logic, local pixel data storage, and a new mechanism to drain triggered hits from the Double-Column. An overview of the new chip will be given with particular emphasis on the new digital logic architecture and possible variations. The new interface needed to configure and operate the chip will also be described.

The adaptive gain integrating pixel detector (AGIPD): A detector for the European XFEL. development and status

The European XFEL under construction in Hamburg will provide fully coherent, 100 fs long X-ray pulses, with 1012 photons at 12 keV. The high intensity per pulse will allow recording diffraction patterns of single particles or small crystals in a single shot. As a consequence the 2D detectors have to cope with a large dynamic range in the images (one to 104 photons/pixel). An additional challenge is the European XFEL machine: an Electron bunch train with 10 Hz repetition rate, consisting of up to 3,000 bunches with a 200 ns spacing. This means that recorded images have to be stored inside the pixel during the bunch trains and read out between bunch trains. In order to meet these requirements, the European XFEL has launched 3 detector development projects. The AGIPD project is a collaboration between DESY, PSI and the Universities of Bonn and Hamburg. The goal is a 1000 ? 1000 pixel detector, with 200 ?m pixel size and a central hole for the primary beam. The ASIC operates in charge integration mode: the output of each pixel preamplifier is proportional to the charge from the sensor generated by the X-rays. The input stage of the pixel cells will have dynamically adjustable gains. The output signal is stored in an analogue pipeline, which has to be a compromise between noise performance and the number of images. 200 to 400 images have to be readout and digitized in the 99.4 ms long bunch gap. The detector will be built of 2 ? 8 fully depleted monolithic silicon sensors with a 2 ? 8 array of CMOS readout chips bump-bonded to these. The interface electronics is designed to process 400 images in 99 msec, without compromising single photon sensitivity or the full dynamic range. Since the ASIC is the linchpin of the project, several MPW runs to test the different aspects in terms of radiation hardness, noise and adaptive switching are submitted. We will give a general overview and report on the current status.