D. Arutinov

An integrated Shunt-LDO regulator for serial powered systems

In this paper, a new type of regulator is proposed for integration in ASICs used in serially powered systems. In the serial powering scheme, modules are placed in series and fed by a constant current source to reduce the IR drop on the cables which increases powering efficiency. At the module level the needed supply voltages are generated redundantly out of the current supply by several parallel operating ASICs with integrated regulation circuitry. A Shunt-LDO regulator has been developed to allow robust and redundant regulator operation and the generation of different supply voltages by parallel placed devices. The Shunt-LDO regulator scheme combines the capability of Low Drop-Out regulators to generate a constant supply voltage with the feature of shunt regulators to assure a constant current flow through the device. The Shunt-LDO regulator has been developed for application in the framework of next generation hybrid pixel detectors used in high energy physics experiments. This circuit has been prototyped in a 130nm CMOS technology, capable of generating voltages in a range of 1.2-1.5V with a minimum drop out voltage of 200mV. The maximum shunt current is 500mA with a load regulation factor corresponding to an output impedance of 30mΩ.

Digital architecture and interface of the new ATLAS Pixel Front-End IC for upgraded LHC luminosity

A new pixel front-end integrated circuit is being developed in a 130 nm technology for use in the foreseen b-layer upgrade of the ATLAS pixel detector. Development of this chip is considered as an intermediate step towards super-LHC upgrade, and also allows having a smaller radius insertable pixel layer. The higher luminosity for which this chip is tuned implies a complete redefinition of the digital architecture logic with respect to the current ATLAS pixel front-end. The new digital architecture logic is not based on a transfer of all pixel hits to the periphery of the chip, but on local pixel logic, local pixel data storage, and a new mechanism to drain triggered hits from the double-column. An overview of the new chip will be given with particular emphasis on the new digital logic architecture and possible variations. The new interface needed to configure and operate the chip will also be described.

The FE-I4 pixel readout system-on-chip resubmission for the insertable B-Layer project

The FE-I4 is a new pixel readout integrated circuit designed to meet the requirements of ATLAS experiment upgrades. The first samples of the FE-I4 engineering run (called FE-I4A) delivered promising results in terms of the requested performances. The FE-I4 team envisaged a number of modifications and fine-tuning before the actual exploitation, planned within the Insertable B-Layer (IBL) of ATLAS. As the IBL schedule was pushed significantly forward, a quick and efficient plan had to be devised for the FE-I4 redesign. This article will present the main objectives of the resubmission, together with the major changes that were a driving factor for this redesign. In addition, the top-level verification and test efforts of the FE-I4 will also be addressed.

Digital architecture of the new ATLAS pixel chip FE-I4

With the high hit rate foreseen for the innermost layers at an upgraded LHC, the current ATLAS Front-End pixel chip FE-I3 [1] would start being inefficient. The main source of inefficiency comes from the copying mechanism of the pixel hits from the pixel array to the end of column buffers. A new ATLAS pixel chip FE-I4 is being developed in a 130 nm technology for use both in the framework of the Insertable B-Layer (IBL) project and for the outer layers of Super-LHC. FE-I4 is made of 80×336 pixels and features a reduced pixel size of 50×250 μm2. In the current design, a new digital architecture is introduced in which hit memories are distributed across the entire pixel array and the pixels organized in regions. In this paper, the digital architecture of FE-I4 is presented as well as the complete data flow.

A serial powering scheme for the ATLAS pixel detector at sLHC

Powering concepts, such as serial powering and DC-DC conversion, are in development for the silicon trackers at sLHC to achieve an efficient power distribution with a minimum volume of cables. This paper will describe the serial powering scheme developed for the upgraded ATLAS pixel detector, with focus on the scheme architecture and on the main components involved: the Shunt-LDO regulator and the protection scheme. Issues connected to system aspects will be discussed, and the advantages in terms of material reduction provided by the proposed serial powering scheme will be presented.

Digital Architecture and Interface of the New ATLAS Pixel Front-End IC for Upgraded LHC Luminosity

A new pixel Front-End Integrated Circuit is being developed in a 130nm technology for use in the foreseen b-layer upgrade of the ATLAS Pixel Detector. Development of this chip is considered as an intermediate step towards super-LHC upgrade, and also allows having a smaller radius insertable pixel layer. The higher luminosity for which this chip is tuned implies a complete redefinition of the digital architecture logic with respect to the current ATLAS pixel Front-End. The new digital architecture logic is not based on a transfer of all pixel hits to the End-of-Column, but on local pixel logic, local pixel data storage, and a new mechanism to drain triggered hits from the Double-Column. An overview of the new chip will be given with particular emphasis on the new digital logic architecture and possible variations. The new interface needed to configure and operate the chip will also be described.

Test results and irradiation performances of 3-D circuits developed in the framework of ATLAS hybrid pixel upgrade

Vertex detectors for High Energy Physics experiments require pixel detectors featuring high spatial resolution, very good signal to noise ratio and radiation hardness. A way to face new challenges of ATLAS/SLHC future hybrid pixel vertex detectors is to use the emerging 3-D Integrated Technologies. However, commercial offers of such technologies are only very few and the 3-D designers choice is then hardly constrained. Moreover, as radiation hardness and specially SEU tolerance of configuration registers is a crucial issue for SLHC vertex detectors and, as commercial data on this point are always missing, a reliable qualification program is to be developed for any candidate technology. We will present the design and test (including radiation tests with 70 kV, 60W X-Ray source and 24 GeV protons) of Chartered, 130nm Low Power 2-D chips realized for this qualification.

Upgrades of the HL-LHC/ATLAS hybrid pixels detector: Test results of the first 3D-IC prototype

Vertex detectors for High Energy Physic experiments require pixel detectors featuring high spatial resolution, very good signal to noise ratio and radiation hardness. A way to face new challenges of the upgrades of HL-LHC/ATLAS future hybrid pixel vertex detectors is to use the emerging 3D Integrated Technologies. However, commercial offers of such technologies are only very few and the 3D designers choice is then very much constrained. Moreover, as radiation hardness and in particular SEU tolerance of configuration registers is a crucial issue for HL-LHC vertex detectors and, as commercial data on this point are always missing, a reliable qualification program is to be developed for any candidate technology. We will present the test results of GlobalFoundries, 130 nm chips processed by Tezzaron Company, submitted within the 3D-IC consortium. Reliability and influence of these 3D connections on integrated devices behavior has also been addressed by tests.

SEU tolerant memory design for the ATLAS pixel readout chip

The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. For this design, configuration memories are based on the DICE latches where layout considerations are followed to improve the tolerance to SEU. Tests have shown that DICE latches for which layout approaches are adopted are 30 times more tolerant to SEU than the standard DICE latches. To prepare for the new pixel readout chip planned for the future upgrades, a prototype chip containing 512 pixels has been designed in a 65 nm CMOS process and a new approach is adopted for SEU tolerant latches. Results in terms of SEU and TID tolerance are presented.

The design for test architecture in digital section of the ATLAS FE-I4 chip

This paper describes an original Design-for-Test (DfT) architecture implemented in the ATLAS FE-I4 pixel readout System-on-Chip (Soc) to accommodate the higher quality demands of future generation LHC detectors. To ensure that the highest possible number of fault-free devices is used for the detector construction, the so-called production test to detect faulty devices after the manufacturing has to be executed. For that reason, we devised a straightforward and effective DfT circuitry inside the digital part of the FE-I4 that will enable high fault coverage of potential structural faults while maintaining the performance and area penalties of the entire design negligible.