K. Kiyoyama

Three-Dimensional Hybrid Integration Technology of CMOS, MEMS, and Photonics Circuits for Optoelectronic Heterogeneous Integrated Systems

We have developed a new 3-D hybrid integration technology of complementary metal-oxide-semiconductors, microelectromechanical systems (MEMS), and photonics circuits for optoelectronic heterogeneous integrated systems. We have overcome the fabrication difficulties of optoelectromechanical and microfluidics hybrid integration. In order to verify the applied 3-D hybrid integration technology, we fabricated a 3-D optoelectronic multichip module composed of large-scale integration (LSI), MEMS, and photonics devices. The electrical chips of amplitude-shift keying (ASK) LSI, passive, and pressure-sensing MEMS were mounted onto an electrical Si interposer with through-silicon vias (TSVs) and microfluidic channels. Photonics chips of vertical-cavity surface-emitting lasers and photodiodes were embedded into an optical Si interposer with TSVs. The electrical and optical interposers were precisely bonded together to form a 3-D optoelectronic multichip module. The photonics and electrical devices could communicate via TSVs. The photonics devices could be connected via an optical waveguide formed onto the optical interposer. Microfluidic channels were formed into the interposer by a wafer-direct bonding technique for heat sinking from high-power LSIs. In this paper, we evaluated the basic functions of individual chips of LSI, MEMS, and photonics devices as they were integrated into the 3-D optoelectronic multichip module to verify the applied 3-D hybrid integration technology. LSI, passive, MEMS, and photonics devices were successfully implemented. The 3-D hybrid integration technology is capable of providing a powerful solution for realizing optoelectronic heterogeneous integrated systems.

New heterogeneous multi-chip module integration technology using self-assembly method

We have newly proposed heterogeneous multi-chip module integration technologies in which MEMS and LSI chips are mounted on Si or flexible substrates using a self-assembly method. A large numbers of chips were precisely and simultaneously self-assembled and bonded onto the substrates with high alignment accuracy of approximately 400 nm. Thick MEMS and LSI chips with a thickness of more than 100 mum were electrically connected by unique lateral interconnections formed crossing over chip edges with large step height. We evaluated fundamental electrical characteristics using daisy chains formed crossing over test chips which were face-up bonded onto the substrates by the self-assembly. We obtained excellent characteristics in these daisy chains. In addition, RF test chips with amplitude shift keying (ASK) demodulator and signal processing circuits were self-assembled onto the substrates and electrically connected by the lateral interconnections. We confirmed that these test chips work well.

3D heterogeneous opto-electronic integration technology for system-on-silicon (SOS)

We proposed 3D heterogeneous opto-electronic integration technology for system-on-silicon (SOS). In order to realize 3D opto-electronic integrated system-on-silicon (SOS), we developed novel heterogeneous integration technology of LSI, MEMS and optoelectronic devices by implementing 3D heterogeneous opto-electronic multi-chip module composed with LSI, passives, MEMS and optoelectronic devices. The electrical interposer mounted with amplitude shift keying (ASK) LSI, LC filter and pressure-sensing MEMS chips and the optical interposer embedded with vertical-cavity surface-emitting laser (VCSEL) and photodiode (PD) chips are precisely bonded to form 3D opto-electronic multi-chip module. Opto-electronic devices are electrically connected via through-silicon vias (TSVs) which were formed into the interposers. Micro-fluidic channels are formed into the interposer by wafer direct bonding technique. 3D heterogeneous opto-electronic multi-chip module is successfully implemented for the first time.

Impact of remnant stress/strain and metal contamination in 3D-LSIs with through-Si vias fabricated by wafer thinning and bonding

Wafer thinning and formation of through-Si via (TSV) and metal microbump are key processes in 3D LSI fabrication. However, it might introduce mechanical stress and crystal defects in thinned wafers. In addition, Cu for TSV and microbump might introduce metal contamination in thinned Si substrate. Then the impact of mechanical stress and metal contamination in the thinned Si substrate has been investigated. The remnant stress left after wafer thinning was evaluated by micro-Raman spectroscopy (µRS) and XPS. It was found that the mechanical stress remained in the back surface of Si substrate after wafer thinning and a part of this mechanical stress appeared in the surface of Si substrate. The metal contamination in such thinned Si substrate has been evaluated by a C-t method. It was found that the carrier generation lifetime was degraded by Cu diffused into Si substrate at relatively low temperature of 200 °C. The mechanical stress/strain in the thinned Si substrate after wafer bonding was also evaluated to investigate the influences of metal microbumps to the thinned Si substrate. It was found that the local mechanical stress was generated in the Si substrate surface by the microbumps. This local stress caused a 3% change in the ON current of MOS transistor.

A Cavity Chip Interconnection Technology for Thick MEMS Chip Integration in MEMS-LSI Multichip Module

We develop a cavity chip interconnection technology for thick microelectromechanical systems (MEMS) chip integration. The cavity chip comprising Cu through-silicon via and Cu beam-lead wire was fabricated by micromachining processes. The cavity chip could easily connect a thick MEMS chip with a high step height of more than a few hundred micrometers without changing the circuit design of MEMS chip and complicated extra process. Fundamental characteristics are successfully obtained from a pressure-sensing MEMS chip of 360- thickness, where the MEMS chip was connected to a Si substrate by the cavity chip without degrading brittle sensing elements. This interconnection technology would provide a good solution for thick MEMS chip integration with high flexibility.

A very low area ADC for 3-D stacked CMOS image processing system

This paper presents a very small circuit area analog-to-digital converter (ADC) for three-dimensional (3-D) stacked CMOS image processing system. To realize high-speed image sensor, we have proposed a block-parallel signal processing with 3-D stacked structure. The proposed block-parallel analog signal processing elements contains CMOS image sensor, correlated double sampling (CDS) array, and ADC array. Each circuit layer is vertically stacked and electrically connected by through-Si vias (TSVs), which can improve sensor performance. On the other hand, the block-parallel system requires ADC with extremely low-power and small circuit area. Therefore, the trade-off among area, power dissipation and conversion speed is important factor, and critical challenge. To achieve extremely low circuit area and low power dissipation, ADC designed in the prototype chip for fundamental evaluation employed the time interleaved charge-redistribution successive approximation (SAR) method. An implemented 9-bit prototype in a 90 nm CMOS technology occupies 100×100 μm2, achieves an ENOB of 7.28 bit at a conversion rate of 4 MS/s. The power dissipation is 381μW with supply voltage of 1.0V and 4 MS/s conversion rate.

Die-Level 3-D Integration Technology for Rapid Prototyping of High-Performance Multifunctionality Hetero-Integrated Systems

We proposed a die-level 3-D integration technology for rapid prototyping of high-performance multifunctionality hetero-integrated systems. Commercially available 2-D chips with different functions and sizes could be processed and integrated in die level. To realize the die-level 3-D integration, fine-sized backside through silicon via (TSV) and novel detachable technologies are developed. In this paper, we demonstrated a prototype 3-D stacked image sensor system using the die-level 3-D integration technology. Three different functional chips of CMOS image sensor, correlated double sampling, and analog-to-digital converter, which were fabricated by different technologies, were processed to form fine-sized backside Cu TSV of 5- μm diameter and metal microbumps in die level. Each chip was sequentially stacked after evaluating the basic function to form a known-good-die 3-D stacked system. The fundamental characteristics of each functional chip were successfully evaluated in the fabricated prototype 3-D stacked image sensor system.

A parallel ADC for high-speed CMOS image processing system with 3D structure

In this paper, we describe the fundamental study of a parallel signal processing circuit, which includes a pixel circuit and a parallel analog-to-digital converter (ADC) with hierarchical correlated double sampling (CDS). To realize high speed image capturing sensor, we have proposed a block-parallel signal processing with three-dimensional (3D) structure. Using 3D structure, the different function layers are stacked vertically and interconnected electrically by through-Si vias (TSVs), which can improve sensor performance and signal band width. On the other hand, the fixed pattern noise (FPN), caused by the circuit device variation, becomes a critical challenge. Experiments on the fabricated pixel circuit have been implemented in a single-layer (two-dimensional) 0.18-µm CMOS image sensor technology. With the analog CDS, the FPN of pixel circuit is reduced by 8.6%. To eliminate the FPN of parallel ADC, a digital CDS technique is implemented. The proposed ADC with digital CDS is designed in a two-dimensional 0.18-µm CMOS technology. The ADC design, including an 8-bit memory, a 6-bit memory, a subtraction circuit, and a comparator, occupies 100×100µm2 area and 0.9mW with supply voltage 1.8 V and 1 MS/s conversion rate. The functional simulation and measurement results confirm that our techniques can effectively reduce fixed pattern noise.

A novel SPRAM (SPin-transfer torque RAM)-based reconfigurable logic block for 3D-stacked reconfigurable spin processor

A novel reconfigurable logic block with SPRAM (spin-transfer torque RAM) is demonstrated. Magnetic elements of 50 times 200 nm2 in area and CMOS logic are fully integrated. Laboratory experimental results show that our reconfigurable logic block achieves 25 MHz read out operation with the magnetic resistance of 1.62 kOmega (parallel) and the MR ratio is 91.7 %.

3D integration technology for 3D stacked retinal chip

To recover visual sensation of blind patients, we have proposed a novel three dimensionally (3D) stacked retinal prosthesis chip in which several LSI chips such as consisting of photodetector, signal processing circuit and stimulus current generator are vertically stacked and electrically connected using 3D integration technology. In this work, we developed several key process for realizing 3D stacked retinal prosthesis chip. Fine sized Cu TSV of 10 µm width and 30 µm depth was successfully formed from the back side of the thinned prosthesis chip. The prosthesis chip with the back side Cu TSVs was flip-chip bonded to Si substrate/flexible substrate through Cu/Sn micro-bumps for evaluating the feasibility of 3D integration technology.