H. Kino

Wafer thinning, bonding, and interconnects induced local strain/stress in 3D-LSIs with fine-pitch high-density microbumps and through-Si vias

Mechanical strain/stress and crystal defects are produced in extremely thin wafers (thickness ∼10 µm) of 3D-LSIs not only during wafer thinning, but also after wafer bonding using fine-pitch, high-density microbumps and curing. Furthermore, the metal of through-Si via (TSV) and microbump not only becomes the cause of contamination, but also induces strain/stress (due to the difference in the co-efficient of thermal expansion (CTE) between Si and metal) in thinned Si substrate. X-ray photoelectron spectroscopy (XPS) results showed that the crystal quality of Si is highly deteriorated in the ultra-poly ground (UPG) surface after wafer thinning and stress relief. Micro-Raman spectroscopy (µRS) data revealed that a local tensile strain amount to 1.8 GPa was induced by 4×4 µm2 square sized Si microbumps in 10 µm-thick LSI wafers after bonding and curing. We have noticed that this locally induced strain/stress caused more than 10% change in the ON current of p-MOS transistor. CuSn microbumps have also induced strain/stress at Si wafer surface, and it penetrates deeper for larger bump size and wider for smaller bump pitch.

Impact of remnant stress/strain and metal contamination in 3D-LSIs with through-Si vias fabricated by wafer thinning and bonding

Wafer thinning and formation of through-Si via (TSV) and metal microbump are key processes in 3D LSI fabrication. However, it might introduce mechanical stress and crystal defects in thinned wafers. In addition, Cu for TSV and microbump might introduce metal contamination in thinned Si substrate. Then the impact of mechanical stress and metal contamination in the thinned Si substrate has been investigated. The remnant stress left after wafer thinning was evaluated by micro-Raman spectroscopy (µRS) and XPS. It was found that the mechanical stress remained in the back surface of Si substrate after wafer thinning and a part of this mechanical stress appeared in the surface of Si substrate. The metal contamination in such thinned Si substrate has been evaluated by a C-t method. It was found that the carrier generation lifetime was degraded by Cu diffused into Si substrate at relatively low temperature of 200 °C. The mechanical stress/strain in the thinned Si substrate after wafer bonding was also evaluated to investigate the influences of metal microbumps to the thinned Si substrate. It was found that the local mechanical stress was generated in the Si substrate surface by the microbumps. This local stress caused a 3% change in the ON current of MOS transistor.

High density 3D LSI technology using W/Cu hybrid TSVs

High density 3D LSI technology using W/Cu hybrid through silicon vias (TSVs) has been proposed. Major reliability issues attributed to W/Cu hybrid TSVs in high density 3D LSIs such as (i) thermo-mechanical stress exerted by W TSVs used for signal lines and Cu TSVs used for power/ground lines in active Si, (ii) external gettering (EG) role played by sub-surface defects in thinned Si substrate, and (iii) effect of local stress induced by μ-bumps on device characteristics are discussed. By annealing at the temperature of ≥300°C, both Cu (via size ≤10µm) and W (via size ≤1µm) square TSVs induce only compressive stress at small TSV spacing which will seriously affect the mobility in active Si area, and thus device characteristics. Large compressive stress not only leads to extrusion and peeling of TSV metal, but also die cracking, and it will adversely impact on the reliability of 3D-LSIs. Then it was proposed to increase the TSV pitch to larger than twice of TSV size to avoid these adverse effects in high density 3D-LSI. Sub-surface defects at dry polished (DP) surface well act as potential EG sites for Cu contamination. Influences of mechanical stress induced by μ-bumps on device characteristics were also evaluated and ultra-small size In-Au μ-bump technology has been developed to minimize the influences of μ-bumps on device characteristics.

Ultrafast parallel reconfiguration of 3D-stacked reconfigurable spin logic chip with on-chip SPRAM (SPin-transfer torque RAM)

We have developed novel 3D-stacked reconfigurable spin logic chip having ultrafast on-chip SPRAM to overcome drawbacks of conventional reconfigurable LSIs. Two reconfigurable spin logic chips were carefully designed and successfully stacked using 3D integration technology. From the SPRAM cell evaluation, the fastest write speed of 5 ns was obtained in the circuits. To realize higher performance reconfigurable LSIs, parallel reconfiguration was fully demonstrated for the stacked reconfigurable spin logic chips for the first time. Both ultrafast on-chip SPRAM and 3D-stacked structure will open a new era of reconfigurable LSIs.

Cu lateral interconnects formed between 100-µm-thick self-assembled chips on flexible substrates

A very new interconnection method, namely Cu lateral interconnection is proposed and tested for the heterogeneous multi-chip module integration in which MEMS and LSI chips are self assembled onto the flexible substrate. Here, the lateral interconnects runs between a few hundred microns thick chip and the Si or flexible substrates as well as at inter chip level. These Cu lateral interconnects were fabricated via conventional electroplating technique. As formed single as well as daisy chain lateral interconnects (both are crossing over the thick test chips that are face-up bonded onto the flexible substrates by self-assembly) were characterized for their electrical characteristics. We have obtained a low resistance values for the Cu lateral interconnects which are close to the calculated values. Further, a module contains RF test chips that are interconnected by this unique Cu lateral interconnections has been tested for the operation.

Impacts of static and dynamic local bending of thinned Si chip on MOSFET performance in 3-D stacked LSI

A three-dimensional (3-D) LSI has many lots of through-Si vias (TSVs) and metal microbumps to achieve electrical connections between stacked thinned LSI chips, and also has organic adhesives to obtain completely bonded thinned LSI chips. However, these elements, especially microbumps and organic adhesives, induce static and dynamic local bending of the thinned LSI chips. In this study, for the first time, we investigated impacts of the static and dynamic local bending on MOSFET characteristics using a novel test structure.

Multiple optical stimulation to neuron using Si opto-neural probe with multiple optical waveguides and metal-cover for optogenetics

We have developed a Si opt-neural probe with multiple waveguides and metal cover for highly accurate optical stimulation. This neural probe had 16 recording sites, three optical waveguides, and metal cover for suppressing light leakage. We evaluated electrochemical properties of the recording sites, and confirmed that the neural probe had suitable characteristics for neural recording. We also demonstrated the optical stimulation to the neurons expressing ChR2 using our probe. As a result, we succeeded multisite optical stimulation, and observed that no light leakage from the optical waveguides because of the metal cover. From in vivo experiments, we successfully recorded optically modulated local field potential using the fabricated Si neural probe with optical waveguides. Moreover, we applied current source density analysis to the recorded LFPs. As a result, we confirmed that light induced membrane current sink in locally stimulated area. Our Si opto-neural probe with multiple optical waveguides and metal-cover is one of the most versatile tools for optogenetics.

Temporary spin-on glass bonding technologies for via-last/backside-via 3D integration using multichip self-assembly

In this study, we proposed and demonstrated self-assembly-based via-last/backside-via 3D integration using a temporary spin-on glass (SOG) bonding technology. A hydrogenated amorphous silicon (a-Si:H) was employed as a debonding layer. Known good dies (KGDs) were precisely self-assembled right side up on an electrostatic carrier wafer by surface tension of water, and then, the KGDs were fixed by applying DC voltage to the carrier. After that, the KGDs were temporarily bonded and transferred to another support glass wafer on which the a-Si:H and SOG layers were deposited. After multichip thinning, Cu-TSVs were formed on the KGDs. The resulting TSV daisy chains showed good electrical characteristics. The KGDs can be debonded with a 308-nm laser and transferred again to target interposer wafers.

Impacts of Microbump-Induced Local Bending Stress in 3D-LSI

1 Dept. of Bioengineering and Robotics, Graduate School of Engineering, Tohoku Univ. 6-6-01 Aza-Aoba, Aramaki, Aoba-ku, Sendai 980-8579, Japan Phone: +81-22-795-6909 E-mail: link@lbc.mech.tohoku.ac.jp 2 New Industry Creation Hatchery Center (NICHe), Tohoku Univ. 3 Association of Super-Advanced Electronics Technologies (ASET) 4 Dept. of Biomedical Engineering, Graduate School of Biomedical Engineering, Tohoku Univ.

Plasma assisted multichip-to-wafer direct bonding technology for self-assembly based 3D integration

We demonstrated plasma-assisted multichip-to-wafer direct bonding for self-assembly based 3D integration processes. We mainly evaluated the bonding yields and bonding strengths of dies obtained by multichip-to-wafer direct oxide-oxide bonding, and compared with wafer-to-wafer direct oxide-oxide bonding in their bonding properties. In this study, we employed thermal oxide and chemical mechanical polish (CMP)-treated oxide formed by plasma-enhanced chemical vapor deposition (PECVD) with tetraethyl orthosilicate (TEOS) as bonding interfaces, and in addition, N2 or Ar plasmas were used for the surface activation. We finally introduce multichip-to-wafer direct oxide-oxide bonding between self-assembled dies and wafers having the PECVD-oxide layer.