E. Gili

Asymmetric gate-induced drain leakage and body leakage in vertical MOSFETs with reduced parasitic capacitance

Vertical MOSFETs, unlike conventional planar MOSFETs, do not have identical structures at the source and drain, but have very different gate overlaps and geometric configurations. This paper investigates the effect of the asymmetric source and drain geometries of surround-gate vertical MOSFETs on the drain leakage currents in the OFF-state region of operation. Measurements of gate-induced drain leakage (GIDL) and body leakage are carried out as a function of temperature for transistors connected in the drain-on-top and drain-on-bottom configurations. Asymmetric leakage currents are seen when the source and drain terminals are interchanged, with the GIDL being higher in the drain-on-bottom configuration and the body leakage being higher in the drain-on-top configuration. Band-to-band tunneling is identified as the dominant leakage mechanism for both the GIDL and body leakage from electrical measurements at temperatures ranging from -50 to 200/spl deg/C. The asymmetric body leakage is explained by a difference in body doping concentration at the top and bottom drain-body junctions due to the use of a p-well ion implantation. The asymmetric GIDL is explained by the difference in gate oxide thickness on the vertical <110> pillar sidewalls and the horizontal <100> wafer surface.

Shallow junctions on pillar sidewalls for sub-100-nm vertical MOSFETs

A simple process for the fabrication of shallow drain junctions on pillar sidewalls in sub-100-nm vertical MOSFETs is described. The key feature of this process is the creation of a polysilicon spacer around the perimeter of the pillar to connect the channel to a polysilicon drain contact. The depth of the junction on the pillar sidewall is primarily determined by the thickness of the polysilicon spacer. This process is CMOS compatible and, hence, facilitates the integration of a sub-100-nm vertical MOSFET in a planar CMOS technology using mature lithography. The fabricated transistors have a subthreshold slope of 95 mV/dec (at VDS=1 V) and a drain-induced barrier lowering of 0.12 V

Depletion-isolation effect in vertical MOSFETs during the transition from partial to fully depleted operation

A simulation study is made of floating-body effects (FBEs) in vertical MOSFETs due to depletion isolation as the pillar thickness is reduced from 200 to 10nm. For pillar thicknesses between 200-60nm, the output characteristics with and without impact ionization are identical at a low drain bias and then diverge at a high drain bias. The critical drain bias V/sub dc/ for which the increased drain-current is observed is found to decrease with a reduction in pillar thickness. This is explained by the onset of FBEs at progressively lower values of the drain bias due to the merging of the drain depletion regions at the bottom of the pillar (depletion isolation). For pillar thicknesses between 60-10nm, the output characteristics show the opposite behavior, namely, the critical drain bias increases with a reduction in pillar thickness. This is explained by a reduction in the severity of the FBEs due to the drain debiasing effect caused by the elevated body potential. Both depletion isolation and gate-gate coupling contribute to the drain-current for pillar thicknesses between 100-40nm.

CMOS-compatible vertical MOSFETs and logic gates with reduced parasitic capacitance

This paper reports electrical results on CMOS-compatible vertical transistors and logic gates with reduced overlap capacitance. It is shown that surround-gate MOSFETs, produced using the fillet local oxidation process (FILOX), have lower gate/drain overlap capacitance and consume less silicon area than comparable lateral MOSFETs. Novel logic gate structures, based on partially removing the polysilicon surround gate, are described and characterised.

Electrical characteristics of single, double & surround gate vertical MOSFETs with reduced overlap capacitance

The vertical MOSFET structure is one of the solutions for reducing the channel length of devices under 50 nm. Surround gate structures can be realized which offer improved short channel effects and more channel width per unit silicon area. In this paper, a low overlap capacitance, surround gate, vertical MOSFET technology is presented, which uses fillet local oxidation (FILOX) to reduce the overlap capacitance between the gate and the drain on the bottom of the pillar. Electrical characteristics of surround gate n-MOSFETs are presented and compared with results from single gate and double gate devices on the same wafer. The devices show good symmetry between the source on top and source on bottom configuration. The short channel effects of the surround gate MOSFETs are investigated.

A technology for building shallow junction MOSFETs on vertical pillar walls

This work addresses a fundamental problem of vertical MOSFETs, that is, inherently deep junctions that exacerbate short channel effects (SCEs). Due to the unconventional asymmetric junctions depth in vertical MOSFETs, it is necessary to look separately at the influence of each junction especially the drain junction on the potential distribution in the channel and hence the SCEs. A self-aligned shallow junction is easily formed at the bottom of a conventional vertical pillar but in order to further suppress the SCEs we explore the formation of a shallow drain junction on the top. A self-aligned oxide region, or junction stop (JS) is formed at the top of the pillar and acts as a hard mask to allow the formation of a shallow drain. The efficacy of this approach to forming shallow junction MOSFETs on vertical pillar walls is demonstrated by simulation with the influence of JS on SCEs clearly shown. Finally, the electrical performance of experimental JS devices is described and discussed in the context of characterization and modeling