M. Masetti

Design of a VLSI very high speed reconfigurable digital fuzzy processor

4 m’gger +tem in High Energv Physics Experiments (HEPEJ has to decide, in frw +s, if the data related to a nuclear event have to be stored or not. Normally. these data, are composed of a bit map where the track coordinates are stored. The possibiliv to use a suitable Fuzq Processor for HEPE has been investigated and the simulations show that a fast fi processor can solve. in many cases. the trigger problem. At the moment a 4 input 50 Mega Fuzzy Inference per Second (MFIPS) Fuzqv Processor has been realized in K!.YI 1.0 w CMOS technologv using the Cadence CAD we got b-v Eurochip. This processor has been tested and the pdiminaty results confirm that it works properly. It is a first reiease of thejinai high speed processor that will be composed of a preprocessor unit and a high speed processor core. The preprocessor is designed to reject the non-active rules [I] while the core processor is an improvement of the previous high speed reconfigurable hardware architecture therefore, the infenmce speed is increased. This research is in progress since these days enough fast and Jlexible Fu.q Processors are not available on the market 121.

VLSI design and realisation of a 4 input high speed fuzzy processor

This paper describes the architecture of a VLSI fuzzy chip designed to run at very high speed: the processing rate is 320 ns when 4 inputs are processed, whichever is the fuzzy system. This processing rate is higher if less than 4 inputs are processed and reaches 100 ns for two inputs. The chip has been designed in 0.7 /spl mu/m CMOS technology, its architecture is pipeline and only the actives rules are processed. To do that the fuzzy system to be processed is first converted in an equivalent one where all the rules are present and then it is loaded in the chip memory. Because of the dimension of the chip rule memory it is possible to construct such a chip when the 4 inputs have no more than 7 Membership Functions, MFs, for each input and the overlapping of the input MFs is not higher than two. The design has been done in VHDL language and it has been synthesized by the Cadence Opus SW obtained via Europractice. This chip has been sent to the ES2 foundry last december to be constructed, we received it back at the end of February and recently it has been successfully rested. At the end of the paper the chip layout is described.

Design of a family of VLSI high speed fuzzy processors

This paper describes the architecture of two VLSI Fuzzy chips designed to run at very high speed: 50 Mega Fuzzy Inference per Second (MFIPS) at least. The two projects differ in the number of inputs; one processes 2-4 seven bit inputs while the other one 8-16 seven bit inputs. The two chips have been designed for applications in High Energy Physics Experiments (HEPE) where the apparatus, called trigger device, needs to discriminate different nuclear events in few microseconds. So far most of the fuzzy logic applications do not require high speed because not required by the industrial applications, therefore they have been done by implementing the fuzzy system on microprocessors, DSPs, or on commercial fuzzy chips which do not have very high speed performances like those necessary for HEPE. In the first phase of our research 1.0 /spl mu/m VLSI fuzzy chip a prototype with four 7 bit inputs and one output running at 50 MFIPS was designed and constructed whose processing rate depends upon the number of rules of the fuzzy system. To further increase the speed we have faced the problem of processing, when possible, only the active fuzzy rules which are a few percent of the total ones.

Architecture of a 50 MFIPS fuzzy processor and the related 1 /spl mu/m VLSI CMOS digital circuits

This paper deals with two problems: the first concerns the design of the HW architecture of a high speed fuzzy processor that can work at 50 Mega fuzzy inference per second (MFIPS). It has eight 7 bit inputs and one 7 bit output. It is foreseen to apply it to a trigger device in HEP (High Energy Physics) experiments, the second one concerns the 1 /spl mu/m CMOS VLSI design of the fuzzification and inference process, the MIN-MAX and the defuzzifier circuits, using the ES2 standard cells, which work with a delay less than 20 ns. These circuits have already been realized and tested. The design has been done using Cadence tools we got from Eurochip. At present a 4 input fuzzy processor has been fully designed and it has been recently sent to ES2 to be realized. Fuzzy processors that run at this speed are not available on the market and this is the innovative feature of this design.

Test results of the ALICE SDD electronic readout prototypes

The first prototypes of the front-end electronic of the ALICE silicon drift detectors has been designed and tested. The integrated circuits have been designed using state-of-theart technologies and, for the analog parts, with radiation-tolerant design techniques. In this paper, the test results of the building blocks of the PASCAL chip and the first prototype of the AMBRA chip are presented. The prototypes fully respect the ALICE requirements; owing to the use of deep-submicron technologies together with radiationtolerant layout techniques, the prototypes have shown a tolerance to a radiation dose much higher than the one foreseen for the ALICE environment. Summary The design of the readout electronic for the ALICE silicon drift detector is a very challenging task, due on one side to the huge amount of data produced by those detectors (256 10-bit words for each detector anode, in the case of the ALICE SDDs ) and on the other hand to the stringent constraints in term of space, power consumption and radiation hardness. The chosen architecture is based on 2 integrated circuits, PASCAL and AMBRA. It works in two different phases: during the acquisition phase the detector signal is amplified and stored into a fast analogue memory; when the trigger signal validates the data, the readout phase starts and the analogue information in the memory is

Design and realization of a two input fuzzy chip running at a rate of 80 ns

A VLSI fuzzy chip with two 7 bit inputs has been designed to run at a rate of 80 ns. The chip has been designed in 0.7 /spl mu/m CMOS technology and to reach such a speed the architecture is pipelined and only the active rules are processed. The design uses the VHDL as a front-end tool and has been synthesized by the Cadence Opus SW obtained via Europractice using the cell-based digital 0.7 /spl mu/m CMOS ES2 technology library. The chip has been sent to the ES2 foundry to be constructed. The chip size is 14 square mm. The chip has been designed for high energy physics applications.

Short time decision VLSI fuzzy processor

In the recent years numerous examples of industrial and research applications have been done by utilizing Fuzzy Logic. In more details fuzzy processors find most of their applications in control logic fields [1]. Besides that it can be said that once an user has written down some fuzzy rules for describing a particular problem, a related fuzzy algorithm can be created. In general this fuzzy algorithm can be implemented either in SW or HW platforms. Nevertheless, even if Fuzzy Logic is also developing in order to decrease the processing time, the HW/SW implementation of a fuzzy algorithm on commercial fuzzy processors may not give good results in term of speed. Consequently, mainly for high speed applications, dedicated fuzzy processors are required. As far as VLSI implementations [2], many researchers have improved the performances of the HW processors by analog [3], [4], digital [5]-[9] or mixed solutions. The different approaches to the design of the VLSI fuzzy processor architectures are in order to find a trade-off between speed, flexibility and layout silicon area. These are exactly the features we have investigated while designing the architecture of the chip here presented. Particularly, chip dimensions, high speed and membership function shapes have been taken into account during the design feature approach. As far as application fields, the Fuzzy Processor has been designed for future applications in High Energy Physics Experiments (HEPE) fields where high processing rates are a part of the global constraints. In this field a very fast 2 input 1 output fuzzy processor may find many applications as co-processor for problems of particle trajectory recognition.

High-speed VLSI fuzzy processors designed for HEPE

Neural chips now are used in the trigger devices for HEPE. Three years ago we talked the problem of using also fuzzy chip microprocessors because a fuzzy system in principle can work as a neural system and is more flexible. We made them a comparison between the two approaches and the conclusions were: fuzzy chips running at a speed suitable for trigger devices were not available on the market, therefore one should have to design his own VLSI chip while, for the neural solution, one can use commercial chips or design a dedicated VLSI chip; the fuzzy solution requires an expert to develop the fuzzy system, that is the rules, while the neural solution requires a training phase; the fuzzy solution is more flexible because you known its knowledge basis and you can improve on-line the related performances by changing the rules. To day this situation is improved because there are SW tools, called Rule Generators, able to develop a fuzzy system by means of Neural Network or Genetic Algorithms. This paper starts with a comparison between Neural Networks and Fuzzy Logic with the aim to summarize the advantages of using both the HEPE trigger devices, then are described the chips already constructed or designed: a first 1 micrometers VLSI fuzzy chip with four 7 bits input and one output running at 50 Mega Fuzzy Inference per Second therefore its processing rate depends upon the fuzzy system to process; a second one, which will be sent to the foundry next march with four 7 bit inputs running at a rate of 300 ns whichever is the fuzzy system; a third one, now in design phase, with 8 - 16 inputs running at 100 - 50 MFIPS with a rule selector to further reduce the total processing speed.

The VLSI design of a digital fuzzification circuit for a 4 input CMOS fuzzy processor running at a rate of 320 ns

The paper first summarizes the architecture of a VLSI fuzzy processor that can be fabricated in 0.7 /spl mu/m digital CMOS technology. This processor is able to process a four 7-bit input data set every 320 ns. This rate increases up to 100 ns if only two inputs are processed. The innovative feature of this design is the independence of the processing rate from the fuzzy system. The fuzzy chip architecture is pipelined and each step takes 20 ns. We describe in this paper the fuzzification process: in our solution the membership functions (MFs) have a triangular shape, therefore there is a memory where the related points necessary to define the shape are stored. In one pipeline step the MF shape is generated and in the following step the grade of truth /spl alpha/ is computed. In this paper we describe in details the circuit.

Design of a 1.0 /spl mu/m reconfigurable VLSI CMOS fuzzy processor which runs at 100-50 MFIPS with an active rule selector

A trigger system in high-energy physics experiments (HEPE) has to decide, in few /spl mu/s, if the data related to a nuclear event have to be stored or not. Normally, these data, are composed of a bit map where the track coordinates are stored. The possibility to use a suitable fuzzy processor for HEPE has been investigated and the simulations show that a fast fuzzy processor can solve, in many cases, the trigger problem. A 4-input 50 mega fuzzy inference per second (MFIPS) fuzzy processor has been fabricated in VLSI 1.0 /spl mu/m CMOS technology using the Cadence CAD we got by Eurochip. This processor has been tested and it works properly. It is a first release of the final high-speed processor that will be composed of a preprocessor unit and a high speed processor core. The preprocessor is designed to reject the nonactive rules while the core processor is an improvement of the previous high speed reconfigurable hardware architecture therefore, the fuzzy inference speed is increased. Moreover it will have 8-16 inputs and one or two outputs.