S. Antinori

Design and Test of the ALICE SDD Data Concentrator Card CARLOSrx

The data concentrator card CARLOSrx is part of the Silicon Drift Detector (SDD) readout chain for the ALICE experiment to be held at CERN. CARLOSrx consists of two 9U times 400 mm VME64 printed circuit boards with the main purpose of receiving data coming from 12 SDDs and sending them towards the ALICE data acquisition system (DAQ) after data processing, buffering and formatting. The paper presents the design of the CARLOSrx boards together with the results of the tests performed with the SDD readout chain.

Implementation of a bidimensional compressor for a high-energy physics experiment

CARLOSv3 is the third version of a chip that plays a significant role in the data acquisition chain of the A Large Ion Collider Experiment (ALICE) silicon drift detector (SDD). ALICE is one of the foremost high-energy physics experiments (HEPE) conducted within the Large Hadron Collider at CERN, the European Organization for Nuclear Research in Geneva. CARLOSv3 was principally designed and built for the on-line compression of the input dataset originating from a physical bidimensional silicon sensor. To compress a bidimensional dataset, a bidimensional data compressor was required. The compressor was designed for the ALICE SDD Experiment but could be applied to all experiments in which an incoming stream dataset originates from a bidimensional sensor.

Design, realization and test of a digital chip for ALICE ITS experiment

CARLOS v3 (Compression And Run Length encOding subSystem) is the name of the third version of a digital radiation hardened chip that plays a significant role in the data acquisition chain of the ALICE experiment (A Large Ion Collider Experiment) for what concerns the Inner Tracking System (ITS). In particular CARLOS has the purpose of performing an on-line compression on data coming from two half detectors SDDs (Silicon Drift Detectors). In fact data volume of SDD events and trigger rate require the use of an on-line compression device with high performances for what concerns compression coefficient and total throughput. The chip has been tested using a specific PCB (Printed Circuit Board) containing the connectors for probing the ASIC with a pattern generator and a logic state analyzer. The chips have been inserted on the PCB using a ZIF socket, that allowed us to test the 35 packaged samples out of the total amount of bare chips received from the foundry. The test phase has shown that 32 out of 35 chips under test work well. CARLOS v3 has been successfully used in the readout chain implemented at CERN during the August 2003 beam test.

Test and commissioning of the CARLOS control boards for the ALICE Silicon Drift Detectors

This paper presents the test strategy employed during the installation of the CARLOS end ladder boards developed for the Silicon Drift Detectors (SDD) of ALICE. Each CARLOS board compresses the data provided by the front-end electronics of one SDD and sends them via an optical link of 800 Mbit/s to the data concentrator card (CARLOSrx) located in the counting room. The paper describes the integration of the CARLOS boards in the final SDD system, including its cooling and mechanical support, the power supply distribution and the optical interconnections. The results of the tests performed after each step of the installation sequence are reported.

Design and construction of an end-ladder prototype board with a 2-D HW compressor

This paper explains the design and the construction of the prototype of an end-ladder card for the silicon drift detector of a high-energy physics experiment at CERN. The end-ladder performs data reduction, compression, and packing for a data acquisition chain. In particular, the end-ladder card includes a chip whose main function is to execute these tasks. Besides the chips functions, the end-ladder card interfaces with the front-end electronics and processes and transmits the data set received from the front end through an optical channel to the counting room. The paper also describes this chip and the ongoing tests on its production. In addition, the paper shows details of the end-ladder prototype cards design and of the relative tests that are going to be carried out in the near future.

Test of the end-ladder prototype board of the ALICE SDD experiment

The paper presents an end-ladder card prototype of the data acquisition chain of the ALICE SDD experim ent. The prototype includes most of the electronics devices that will be applied to ALICE SDD experiment. The card interface s with the front-end electronics and with the counting roo m detector data link via the interface card named CARLOS_rx. T he end_ladder PCB has been fully tested by providing c ontrol signals and input vectors via a pattern generator a nd by collecting output data via the detector data link.

Design and construction of an ALICE SDD end-ladder prototype board

The paper explains the design and the construction of a prototype of an end-ladder card for the ALICE SDD experiment. The final end-ladder card will receive an input dataset from the front-end electronics and will transmit the elaborated dataset through an optical channel to the counting room. The proposed prototype card includes an actual ALICE SDD end-ladder prototype card with all the components foreseen for the final version. This is designed together with an external larger card with all the testing equipment required for measurements in lab. The end-ladder card matches the final dimensions while the external larger one provides all the connectors and an optical receiver mirror unit for an easy-to-use complete system. The final optical modules are provided into the end-ladder prototype card and are composed of 2-photodiodes and 1-laser single-mode 1310 nm with their single mode fibers. Once the front end dataset enters the prototype, a small size digital rad-hard chip carries out a bidimensional compression and acts as a JTAG switch for the front end electronics. The incoming dataset is then compressed, packed, serialized and output via an 800 Mb/s optical link to the external receiver card of the prototype. The mirror receiver card deserializes the stream and reconstructs the original dataset before being compressed.