M. Muller

Origin of Vt instabilities in high-k dielectrics Jahn-Teller effect or oxygen vacancies

In this paper, an analysis of the trapping in high- dielectrics and its origin is given. It is found that the defect is consistent with oxygen vacancies in monoclinic hafnia. Finally, guidelines are proposed to reduce these instabilities

Improved Vt and Ioff characteristics of NMOS transistors featuring ultra-shallow junctions obtained by plasma doping (PLAD)

We present in this paper a detailed analysis of the electrical behaviour of NMOS transistors with gate lengths down to Lg = 30 nm where the source/drain extensions (SDE) were developed using ultra low energy implantation (As 1 keV) or plasma doping (PLAD) at low bias (1.5 kV). PLAD splits show excellent threshold characteristics in comparison with As 1 keV: delayed Vt roll-down, reduced short channel effect (SCE) and drain induced barrier lowering (DIBL). The Ion/Ioff trade-off analysis reveals a much lower Ioff for comparable gate lengths when using PLAD instead of ULE. These behaviours are explained by a reduced junction depth Xj, which is confirmed by a parameter extraction on transistor characteristics and by analytical modelling.

Towards a better EOT - mobility trade-off in high-k oxide/metal gate CMOS devices

In this paper, we present electrical results on damascene CMOS devices containing a HfO/sub 2/ gate oxide and a TiN/W gate electrode and give a detailed analysis of the performance data and the carrier mobility in both pMOS and nMOS devices. We report on an improvement of the electron mobility compared to recent literature data, which seems to be related to a slightly higher interfacial oxide layer. These findings are very interesting regarding the definition of a good trade-off between mobility and EOT for future CMOS transistors using high-k materials for the gate oxide.

New junction concepts for sub-50 nm CMOS transistors: slim spacers and Ni silicide

In this paper, we evaluate the potential of two concepts aiming at the vertical and horizontal reengineering of the S/D junctions of sub-50 nm-CMOS transistors: slim S/D spacers and Ni silicide. We demonstrate the benefit of the lateral spacer size reduction in terms of device performance. For the junction silicidation with Ni, we find electrically equivalent results while the silicidation depth is reduced by 50% with respect to the Co reference. This will enable the use of shallower S/D junctions giving a maximum DIBL and SCE control - an approach, which is especially interesting in combination with slim spacers.

CMP-less integration of 40nm-gate totally silicided (TOSI) bulk transistors using selective S/D Si epitaxy and ultra-low gates

In this paper, we present an innovative way of fabricating CMOS transistors with totally Ni-silicided (Ni-TOSI) gates without using a CMP step before the full gate silicidation. The combination of the use of a hard-mask-capped ultra-low Si gate with a selective S/D epitaxy step enables us to obtain a well-behaved silicidation of the junctions and the full gate within one single step with minimal gate lengths of 40nm. Moreover, we show that the TOSI PMOS device performances are compatible with the 45nm-node LP requirements. Reliability data is added demonstrating that no additional breakdown mechanisms occur after the TOSI process.

Silicidation induced strain phenomena in totally silicided (TOSI) gate transistors

In this paper, we present a detailed analysis of the performance and transport characteristics in totally Ni silicided (TOSI) devices. For two different TOSI integration schemes, we study transconductance variations of TOSI devices with respect to poly-Si gated devices. We find a clear signature of process induced strain related to the total gate silicidation step which depends largely on the integration scheme used for the fabrication of the TOSI devices.

Fully-depleted SOI CMOS technology using W X N metal gate and HfSi x O y N Z high-k dielectric

This paper describes the fabrication and electrical behavior of a fully-depleted SOI technology using a direct metal gate and high-k dielectric integrated on 300 mm SOI wafers for low power applications. We report ultra-thin FDSOI MOS transistors with WN metal gate (capped with TiN) on HfSiON gate dielectric. Performance at both device and circuit level are demonstrated and compared with TiN midgap metal gate.

Totally Silicided (TOSI) Gates as an evolutionary metal gate solution for advanced CMOS technologies

In this paper, we show that totally silicided (TOSI) gate electrodes offer an interesting and industrially viable option for the integration of metal gate electrodes in advanced CMOS technologies as their integration requires only few modifications with respect to a CMOS standard flow. Moreover, the use of NiSi gives access to an electrode with a tunable mid-gap work function. The potential of TOSI-gate devices is demonstrated by integration and device results including fully operational SRAM cells and reliability data

Dual phase TOSI-gate process on High-K dielectrics in a CMP-less flow

In this paper, we demonstrate for the first time a new original approach of the integration of dual phase totally silicided (TOSI) gates using a close-to-standard CMOS flow without any additional CMP step targeting the use of NiSi for NMOS and Ni2Si for the PMOS gate electrode on high-k dielectrics. The impact of the TOSI-process on the gate stack characteristics is investigated in detail on capacitance, gate leakage and work function data. With respect to poly-Si gated devices we find a significant reduction of the effective oxide thickness in inversion without degradation of the gate leakage statistics. The results emphasize the potential of the integration of TOSI-gates on high-k gate oxides