Alexandre Talbot

50 nm-Gate All Around (GAA)-Silicon On Nothing (SON)-devices: a simple way to co-integration of GAA transistors within bulk MOSFET process

For the first time, both GAA and bulk devices were shown to be operational on the same chip. Not all issues have been solved yet (gate materials, access resistance) but already the first-try results are very encouraging: I/sub on/=170 /spl mu/A//spl mu/m@1.2 V and gate oxide of 20 /spl Aring/. Thanks to the GAA intrinsic immunity to SCE, its DIBL was as small as 10 mV compared with 600 mV on bulk control devices. Calibrating a 2D simulator on this electrical data, the performance of the GAA was estimated to be at least 1500 /spl mu/A//spl mu/m@ 1 V with comfortable gate oxide of 20 /spl Aring/, once having corrected for the large R/sub access/ (/spl sim/3000 /spl Omega/), that was simply due to non-optimal mask layout used in this first device realization.

First 80 nm SON (Silicon-On-Nothing) MOSFETs with perfect morphology and high electrical performance

In this paper, the first 80 nm SON MOSFETs are presented, demonstrating the electrical viability of the SON architecture. The transistors have a 20 nm thick Si-film channel, isolated from the bulk by a 20 nm dielectric layer. The electrical results show significant improvement (/spl sim/30%) compared with bulk reference devices. In particular, drive current and transconductance are improved due to the better effective field-inversion charge compromise, and SCE due to the thinness of the junctions and of the channel. These electrical results are then used to calibrate the ISE simulator and to make predictions on SON performances with more aggressive gate length and Tox. These predictions show the potential of the SON architecture for future CMOS generations.

Highly performant double gate MOSFET realized with SON process

Utilizing the SON (silicon on nothing) process, highly performant double gate devices have been processed in a planar configuration. Two families of devices were obtained (high performance and low power) with very high Ion/Ioff trade off. Drive currents of 1954 /spl mu/A//spl mu/m (Ioff = 283 nA//spl mu/m) and 1333 /spl mu/A//spl mu/m (Ioff = 1 nA//spl mu/m) are obtained at 1.2 V with Tox = 20 /spl Aring/ and Lgate = 70 nm. DIBL is very well controlled, measured below 60 mV for gates as short as 40 nm. These features place our devices among the most performant ever reported.

SON (Silicon-On-Nothing) P-MOSFETs with totally silicided (CoSi/sub 2/) polysilicon on 5 nm-thick Si-films: the simplest way to integration of metal gates on thin FD channels

In this paper, the first SON (Silicon On Nothing) devices with metal gate are presented. Extremely thin fully depleted Si-films are recognized to be integrable with single-metal gate (mid-gap) due to their intrinsically low threshold voltage. In this work we present mid-gap CoSi/sub 2/ metal gate by total gate silicidation on SON transistors with Si-conduction channel thickness down to 5 nm. Due to its architecture and to the continuity between SD areas and the bulk, SON transistors allow deep silicidation processing down to the gate oxide, meaning that no more polysilicon is left. SON PMOS devices were performed with 55 nm CoSi/sub 2/ gate length with 5 nm of Si-channel thickness, and show excellent performances (350 /spl mu/A//spl mu/m I/sub on/ with only 0.1 nA I/sub off/ at -1.4 V with T/sub ox/=20 /spl Aring/). The polydepletion is of course suppressed and the gate resistance (<2 /spl Omega///spl square/) is very competitive for RF applications.

Facet Propagation in Si and SiGe Epitaxy or Etching

The facet propagation during silicon and SiGe epitaxial growth has been studied in terms of morphology and kinetics. Epitaxies were deposited on (001) Si wafers by chemical vapour deposition with the SiH2Cl2/HCl/H2 chemistry. In a similar way the faceting effects during HCl-chemical vapour etching of monocrystalline silicon have been examined. In both cases, the appearance of certain facets in certain experimental conditions has been explained on the basis of the different activation energies of growth kinetics found for the main high density crystal planes. Thus, we demonstrate that this kinetics anisotropy is the root cause of Si epitaxy faceting, and especially of the important {311} facets observed in most of conditions. And finally, we consider that our theoretical frame should be also valid for extended process conditions and various samples configurations.

Performance boost of scaled Si PMOS through novel SiGe stressor for HP CMOS

In this paper, we present a highly-performant PMOS transistor architecture featuring a buried strained SiGe layer (stressor) underneath the Si channel and in between the epitaxially grown Si S/D regions. This stressor together with the shallow trench isolation (STI) induces pseudo-biaxial compressive stress in small devices Si channel. A completely different behaviour compared to bulk-Si devices is shown. Transistors featuring a 50nm gate length, a 1.5nm physical gate oxinitride and an active area width of 0.28/spl mu/m demonstrate drive currents up to 740/spl mu/A//spl mu/m with only 48nA//spl mu/m Ioff at a supply voltage of 1.4V. Those results, regarding the oxide thickness, are in the range of the best ever reported. Moreover, this solution provides easy co-integration possibilities between HP, GP and LP (bulk-like or SON: silicon-on-nothing) devices on the same chip.

Selective SiGeC epitaxy by RTCVD for high performance self-aligned HBT

Selective SiGeC epitaxy is desirable for forming the base of self aligned HBTs. Carbon, incorporated into substitutional sites (C/sub s/), should suppress boron outdiffusion in the base. We show that C/sub s/ incorporation is decreased as temperature or total C concentration is increased, leading to defects in the epitaxy and degradation of the base current. Nevertheless, we were able to grow, selectively, high quality SiGeC films with a C dose high enough to block boron diffusion. This is confirmed by the comparison of static and dynamic results between a C-free and a C-doped SiGe HBT Finally, a state of the art 175 GHz ft/180 GHz f/sub MAX/ HBT with a selective epitaxial SiGeC base is presented.

CMP-less integration of 40nm-gate totally silicided (TOSI) bulk transistors using selective S/D Si epitaxy and ultra-low gates

In this paper, we present an innovative way of fabricating CMOS transistors with totally Ni-silicided (Ni-TOSI) gates without using a CMP step before the full gate silicidation. The combination of the use of a hard-mask-capped ultra-low Si gate with a selective S/D epitaxy step enables us to obtain a well-behaved silicidation of the junctions and the full gate within one single step with minimal gate lengths of 40nm. Moreover, we show that the TOSI PMOS device performances are compatible with the 45nm-node LP requirements. Reliability data is added demonstrating that no additional breakdown mechanisms occur after the TOSI process.

Silicidation induced strain phenomena in totally silicided (TOSI) gate transistors

In this paper, we present a detailed analysis of the performance and transport characteristics in totally Ni silicided (TOSI) devices. For two different TOSI integration schemes, we study transconductance variations of TOSI devices with respect to poly-Si gated devices. We find a clear signature of process induced strain related to the total gate silicidation step which depends largely on the integration scheme used for the fabrication of the TOSI devices.

Dual phase TOSI-gate process on High-K dielectrics in a CMP-less flow

In this paper, we demonstrate for the first time a new original approach of the integration of dual phase totally silicided (TOSI) gates using a close-to-standard CMOS flow without any additional CMP step targeting the use of NiSi for NMOS and Ni2Si for the PMOS gate electrode on high-k dielectrics. The impact of the TOSI-process on the gate stack characteristics is investigated in detail on capacitance, gate leakage and work function data. With respect to poly-Si gated devices we find a significant reduction of the effective oxide thickness in inversion without degradation of the gate leakage statistics. The results emphasize the potential of the integration of TOSI-gates on high-k gate oxides