M. Piendibene

The Associative Memory Serial Link Processor for the Fast TracKer (FTK) at ATLAS

The Fast TracKer (FTK) is an extremely powerful and very compact processing unit, essential for efficient Level 2 trigger selection in future high-energy physics experiments at the LHC. FTK employs Associative Memories (AM) to perform pattern recognition; input and output data are transmitted over serial links at 2 Gbit/s to reduce routing congestion at the board level. Prototypes of the AM chip and of the AM board have been manufactured and tested, in preparation of the imminent design of the final version.

Performance of the AMBFTK board for the FastTracker processor for the ATLAS detector upgrade

Modern experiments at hadron colliders search for extremely rare processes hidden in a very large background. As the experiment complexity and the accelerator backgrounds and luminosity increase we need increasingly complex and exclusive selections. The FastTracker (FTK) processor for the ATLAS experiment offers extremely powerful, very compact and low power consumption processing units for the future, which is essential for increased efficiency and purity in the Level 2 trigger selection through the intensive use of tracking. Pattern recognition is performed with Associative Memories (AM). The AMBFTK board and the AMchip04 integrated circuit have been designed specifically for this purpose. We report on the preliminary test results of the first prototypes of the AMBFTK board and of the AMchip04.

Associative Memory for L1 track triggering in LHC environment

The CDF Associative-Memory device (AM), proven technology developed for the Silicon-Vertex-Trigger at the CDF experiment, is one of the proposed solutions at the LHC for track reconstruction at level-1 in the HL-LHC upgrade, for very high-luminosity conditions (hundreds proton-proton collisions every 25 ns, at 5×1034 cm- 2 sec- 1). This luminosity requires a drastic revision of the existing trigger strategies. In the CMS experiment, one of the identified challenges for future upgrades is the capability of using already at L1 the tracker information to trigger events. Simulation studies show that this can be achieved by correlating hits on two closely spaced silicon strip sensors. This strategy requires massive computing power, to minimize the online execution time of complex tracking algorithms and the “combinatorial challenge.” The AM allows to compare the tracker information of each event to pre-calculated “expectations” (pattern matching) in a so short time that tracks can contribute to the trigger decision. One of the main challenges for the CMS tracker is the latency due to the tracker data distribution to the AM processors. A very parallelized readout architecture and a possible layout are discussed.

Highly Parallelized Pattern Matching Hardware for Fast Tracking at Hadron Colliders

A high-performance “pattern matching” implementation based on the Associative Memory (AM) system is presented. It is designed to solve the real-time hit-to-track association problem for particles produced in high-energy physics experiments at hadron colliders. The processing time of pattern recognition in CPU-based algorithms increases rapidly with the detector occupancy due to the limited computing power and input-output capacity of hardware available on the market. The AM system presented here solves the problem by being able to process even the most complex hadron collider events produced at a rate of 100 kHz with an average latency smaller than 10 μs. The board built for this goal is able to execute ~12 petabyte comparisons per second, with peak power consumption below 250 W, uniformly distributed on the large area of the board.

ATLAS FTK: Fast Track Trigger

A track reconstruction system for the trigger of the ATLAS detector at the Large Hadron Collider is described. The Fast Tracker is a highly parallel hardware system designed to operate at the Level-1 trigger output rate. It will provide high-quality tracks reconstructed over the entire inner detector by the start of processing in the Level-2 trigger. The system is based on associative memories for pattern recognition and fast FPGA’s for track reconstruction. Its design and expected performance under instantaneous luminosities up to 3 10 34 =cm 2 =s are discussed.

FTK: a Fast Track Trigger for ATLAS

We describe the design and expected performance of a the Fast Tracker Trigger (FTK) system for the ATLAS detector at the Large Hadron Collider. The FTK is a highly parallel hardware system designed to operate at the Level 1 trigger output rate. It is designed to provide global tracks reconstructed in the inner detector with resolution comparable to the full offline reconstruction as input of the Level 2 trigger processing. The hardware system is based on associative memories for pattern recognition and fast FPGAs for track reconstruction. The FTK is expected to dramatically improve the performance of track based isolation and b-tagging with little to no dependencies of pile-up interactions.

The Associative Memory System Infrastructures for the ATLAS Fast Tracker

The associative memory (AM) system of fast tracker (FTK) processor has been designed for the tracking trigger upgrade to the ATLAS detector at the Conseil Europeen Pour La Recherche Nucleaire large hadron collider. The system performs pattern matching (PM) using the detector hits of particles in the ATLAS silicon tracker. The AM system is the main processing element of FTK and is mainly based on the use of application-specified integrated circuits (ASICs) (AM chips) designed to execute PM with a high degree of parallelism. It finds track candidates at low resolution which become seeds for a full resolution track fitting. The AM system implementation is based on a collection of large 9U Versa Module Europa (VME) boards, named “serial link processors” (AMBSLPs). On these boards, a huge traffic of data is implemented on a network of 900 2-Gb/s serial links. The complete AM-based processor consumes much less power (~50 kW) than its CPU equivalent and its size is much smaller. The AMBSLP has a power consumption of ~250 W and there will be 16 of them in a crate. This results in unusually large power consumption for a VME crate and the need for complex custom infrastructure in order to have sufficient cooling. This paper reports on the design and testing of the infrastructures needed to run and cool the system which will include 16 AMBSLPs in the same crate, the integration of the AMBSLP inside a first FTK slice, the performance of the produced prototypes (both hardware and firmware), as well as their tests in the global FTK integration. This is an important milestone to be satisfied before the FTK production.

Thin pixel development for the Layer0 of the SuperB Silicon Vertex Tracker

The SuperB asymmetric e⁺ e⁻ collider has been designed to deliver a luminosity greater than 10³⁶ cm⁻² s⁻¹ maintaining moderate beam currents. Comparing to current B-Factories, the reduced center-of-mass boost of the SuperB machine requires an improved vertex resolution to allow precision measurements sensitive to New Physics. Therefore the SuperB Silicon Vertex Tracker will be equipped with an innermost Layer0 with a radius of about 1.5 cm, high granularity, low material budget and able to withstand a background rate of several MHz/cm². We report on the status of the R&D on the different options under study for the Layer0: DNW MAPS, hybrid pixels and thin pixels developed with vertical integration technology.

Enhancement of the ATLAS trigger system with a hardware tracker finder FTK

The existing three-level ATLAS trigger system is deployed to reduce the event rate from the bunch crossing rate of 40 MHz to ~ 200 Hz for permanent storage at the LHC design luminosity of 1034 cm−2 s−1. When the LHC exceeds the design luminosity, the load on the Level-2 trigger system will significantly increase due both to the need for more sophisticated algorithms to suppress background and the larger event sizes. The Fast Tracker is a proposed upgrade to the current ATLAS trigger system that will operate at the full Level-1 accepted rate of 100 kHz and provide high quality tracks at the beginning of processing in the Level-2 trigger, by performing track reconstruction in hardware with massive parallelism of associative memories. The concept design is being advanced and justified with the performance in important physics areas, b-tagging, τ-tagging and lepton isolation. The prototyping with current technology is underway and R&D with new technologies has been started.

The associative memory for the self-triggered SLIM5 silicon telescope

Modern experiments search for extremely rare processes hidden in much larger background levels. As the experiment complexity, the accelerator backgrounds and luminosity increase we need increasingly exclusive selections to efficiently select the rare events inside the huge background. We present a fast, high-quality, track-based event selection for the self-triggered SLIM5 silicon telescope. This is an R&D experiment whose innovative trigger will show that high rejection factors and manageable trigger rates can be achieved using fine-granularity, low-material tracking detectors.