F. M. Giorgi

The Data Acquisition and Transport Design for NEMO Phase 1

The NEMO collaboration proposes to build an underwater neutrino telescope located South-East off the Sicily coast. This paper describes the concepts underlying the communication link design going over the whole data acquisition and transport from the front-end electronics to the module sending data on-shore through a fiber optic link which relies on Dense Wavelength Division Multiplexing. An on-shore board, plugged into a PC, extracts and distributes data both to first-level trigger and control systems. Underwater apparatus monitoring and controls are guaranteed by oceanographic instruments and dedicated sensors, whose data are packed and sent back to shore using the same optical link. The communication is fully bidirectional, allowing transmission of timing and control commands. The architecture described here provides a complete real-time data transport layer between the onshore laboratory and the underwater detector. During winter 2006 a first prototype of the apparatus has been deployed: calibration results from the currently working system are here reported.

The associative memory for the self-triggered SLIM5 silicon telescope

Modern experiments search for extremely rare processes hidden in much larger background levels. As the experiment complexity, the accelerator backgrounds and luminosity increase we need increasingly exclusive selections to efficiently select the rare events inside the huge background. We present a fast, high-quality, track-based event selection for the self-triggered SLIM5 silicon telescope. This is an R&D experiment whose innovative trigger will show that high rejection factors and manageable trigger rates can be achieved using fine-granularity, low-material tracking detectors.

NEMO: A PROJECT FOR A KM3 UNDERWATER DETECTOR FOR ASTROPHYSICAL NEUTRINOS IN THE MEDITERRANEAN SEA

The status of the project is described: the activity on long term characterization of water optical and oceanographic parameters at the Capo Passero site candidate for the Mediterranean km3 neutrino telescope; the feasibility study; the physics performances and underwater technology for the km3; the activity on NEMO Phase 1, a technological demonstrator that has been deployed at 2000 m depth 25 km offshore Catania; the realization of an underwater infrastructure at 3500 m depth at the candidate site (NEMO Phase 2).

Application of a HEPE-oriented 4096-MAPS to time analysis of single electron distribution in a two-slits interference experiment

The Young-Feynman two-slit experiment for single electrons has been carried out by inserting in a conventional transmission electron microscope two nanometric slits and a fast recording system able to measure the electron arrival-time. The detector, designed for experiments in future colliders, is based on a custom CMOS chip of 4096 monolithic active pixels equipped with a fast readout chain able to manage up to 106 frames per second. In this way, high statistic samples of single electron events can be collected within a time interval short enough to guarantee the stability of the system and coherence conditions of the illumination. For the first time in a single electron two-slit experiment, the time distribution of electron arrivals has been measured.

TOPEM: A multimodality probe (PET TOF, MRI, and MRS) for diagnosis and follow up of prostate cancer

Multimodality imaging plays a significant role on specific diagnosis of prostate cancer. An endorectal PET-TOF MRI probe, designed here, allows for improved SNR and NECR with respect to standard imagers, providing better functional diagnosis of prostate diseases.

ATLAS FTK: Fast Track Trigger

A track reconstruction system for the trigger of the ATLAS detector at the Large Hadron Collider is described. The Fast Tracker is a highly parallel hardware system designed to operate at the Level-1 trigger output rate. It will provide high-quality tracks reconstructed over the entire inner detector by the start of processing in the Level-2 trigger. The system is based on associative memories for pattern recognition and fast FPGA’s for track reconstruction. Its design and expected performance under instantaneous luminosities up to 3 10 34 =cm 2 =s are discussed.

FTK: a Fast Track Trigger for ATLAS

We describe the design and expected performance of a the Fast Tracker Trigger (FTK) system for the ATLAS detector at the Large Hadron Collider. The FTK is a highly parallel hardware system designed to operate at the Level 1 trigger output rate. It is designed to provide global tracks reconstructed in the inner detector with resolution comparable to the full offline reconstruction as input of the Level 2 trigger processing. The hardware system is based on associative memories for pattern recognition and fast FPGAs for track reconstruction. The FTK is expected to dramatically improve the performance of track based isolation and b-tagging with little to no dependencies of pile-up interactions.

On-Chip Fast Data Sparsification for a Monolithic 4096-Pixel Device

The paper describes a mixed-mode ASIC composed of a fast readout architecture that interfaces with a matrix of 4096 Monolithic Active Pixel Sensors (MAPS). The matrix has 128 columns and 32 rows of pixels and is divided into 256 regions of 4 times 4 pixels, named macro-pixels (MPs). The chip is an upgrade of a smaller version having 256 pixels that was designed and tested. The two chips were designed via STM 130 nm CMOS technology. The pixel dimension is 50 by 50 mum2 . The work is aimed at improving the design of MAPS detectors with an on-chip fast sparsification system, for particle tracking, to match the requirements of future high-energy physics experiments. The readout architecture implemented is data driven to extend the flexibility of the system, to be also used in first level triggers on tracks in vertex detectors. Simulations indicate that the readout system can cope with an average hit rate up to 100 MHz/cm2 if a master clock of 80 MHz is used, while maintaining an overall efficiency over 99%.

A high efficiency readout architecture for a large matrix of pixels.

In this work we present a fast readout architecture for silicon pixel matrix sensors that has been designed to sustain very high rates, above 1 MHz/mm2 for matrices greater than 80k pixels. This logic can be implemented within MAPS (Monolithic Active Pixel Sensors), a kind of high resolution sensor that integrates on the same bulk the sensor matrix and the CMOS logic for readout, but it can be exploited also with other technologies. The proposed architecture is based on three main concepts. First of all, the readout of the hits is performed by activating one column at a time; all the fired pixels on the active column are read, sparsified and reset in parallel in one clock cycle. This implies the use of global signals across the sensor matrix. The consequent reduction of metal interconnections improves the active area while maintaining a high granularity (down to a pixel pitch of 40 ?m). Secondly, the activation for readout takes place only for those columns overlapping with a certain fired area, thus reducing the sweeping time of the whole matrix and reducing the pixel dead-time. Third, the sparsification (x-y address labeling of the hits) is performed with a lower granularity with respect to single pixels, by addressing vertical zones of 8 pixels each. The fine-grain Y resolution is achieved by appending the zone pattern to the zone address of a hit. We show then the benefits of this technique in presence of clusters. We describe this architecture from a schematic point of view, then presenting the efficiency results obtained by VHDL simulations.

Thin pixel development for the Layer0 of the SuperB Silicon Vertex Tracker

The SuperB asymmetric e⁺ e⁻ collider has been designed to deliver a luminosity greater than 10³⁶ cm⁻² s⁻¹ maintaining moderate beam currents. Comparing to current B-Factories, the reduced center-of-mass boost of the SuperB machine requires an improved vertex resolution to allow precision measurements sensitive to New Physics. Therefore the SuperB Silicon Vertex Tracker will be equipped with an innermost Layer0 with a radius of about 1.5 cm, high granularity, low material budget and able to withstand a background rate of several MHz/cm². We report on the status of the R&D on the different options under study for the Layer0: DNW MAPS, hybrid pixels and thin pixels developed with vertical integration technology.