M. Poletti

Digital synthesis of analog signals for audiometric applications

This paper presents a novel signal generator, based on the direct digital synthesis (DDS) technique, which fulfills the requirements of advanced audiometric systems. The described solutions face two different problems, namely the generation of a finely tunable pure sinewave and the generation of noise signals with controlled spectrum. In order to achieve tuning capabilities down to 1Hz at 20 kHz or 15 /spl mu/Hz at 100 Hz, a fractional division of a 40 MHz master clock with noise shaping of the resulting error is performed. Moreover, for noise generation a novel circuit based on pseudo-random sequences combined with analog SC filters is used.

Design considerations on very high resolution sigma-delta modulators

This paper describes theoretical limits and practical considerations concerning the design of high resolution (SNR>100 dB) sigma-delta A/D converters. By looking at a series of constraints affecting the design of basic devices and building blocks, we discuss important aspects of the theory of high-order single-loop modulators and find limitations to the maximum signal-to-noise ratio as a function of the power consumption and the sampling frequency. Moreover, starting from the theoretical results, we show how to optimize the modulator performance with behavioral simulations.

A CMOS integrated infrared radiation detector for flame monitoring

This paper presents an integrated infrared radiation detector for flame monitoring applications, fabricated in CMOS technology. The system discriminates the radiation of the flickering flame in an oil burner from the steady background radiation generated by the furnace by considering only the harmonic components of the infrared signal in the band from 50 Hz to 250 Hz. In order to maximize the flexibility and the robustness of the system, most of the signal processing is performed in the digital domain. Experimental results on an integrated prototype, confirming the validity of the proposed approach, are reported.

An 0.8 /spl mu/m CMOS mixed analog-digital integrated audiometric system

Modern medical instruments used for audiometric tests (audiometers) require high-quality audio signals and sophisticated signal processing. During audiometric tests, indeed, the human ear is stimulated with complex modulated sinusoidal signals or masking signals (noise), to identify hearing defects or losses that can be corrected with hearing aids. The evolution of hearing aid devices from simple amplification stages to sophisticated equalizers requires a substantial improvement in the quality of the audiometric tests, to accurately customize the frequency response and optimize the hearing defect correction. The audiometers used to date based on analog components, are no longer sufficient in terms of accuracy and precision. This mixed analog/digital integrated audiometric system generates the complete set of audio and control signals required for an exhaustive audiometric test. The block diagram of the chip is shown. The system is divided into five main functional blocks: a standard microprocessor interface (bus), the digital signal generator, switched-capacitor (SC) and continuous-time (CT) filters and two separated analog signal processing channels (Left and Right).

A 147-dB dynamic range electronic attenuator for audiometric applications with on-chip 1-W power amplifier

This paper presents an electronic attenuator for audiometric applications, including an on-chip power amplifier which drives 8 V<inf>pp</inf>on a 7Ω resistive load. The 24 mm²chip, fabricated in a 2 µm high-voltage CMOS process, achieves 147 dB of dynamic range and 80 dB of signal-to-noise ratio, consuming 33 mA from a ±5 V power supply.

A 12 bit A/D interface for a 3D magnetic sensor

This paper presents a high resolution low-power smart system for 3D magnetic field monitoring. The magnetic sensors, integrated on-chip, need a bias current of a few mA to achieve the required resolution. Nevertheless, the proposed 12 bit A/D converter allows pulsed operation of the sensors with a duty cycle as low as 4 10/sup -5/, thus keeping the system power consumption below 1 /spl mu/W. The A/D converter operates with 500 kHz clock frequency and achieves a DNL below 0.2 LSB and an INL below 0.5 LSB in worst case simulations. A prototype of the system has been integrated in a 1.2 /spl mu/m CMOS technology.

Switched-capacitor Litton-code matched filter for satellite ODBH bus

In this paper we present a switched-capacitor matched filter for the satellite on-board data handling (OBDH) Litton coded bus. The proposed filter represents the analog front-end of the bus interface (modem) in the central data management unit (CDMU) and in each remote terminal unit (RTU) of the satellite on-board communication system. The filter consists of a 16-taps switched-capacitor FIR structure, implemented using a mixed serial/parallel architecture which allows optimal performance to be achieved with a minimum number of components. Simulation results confirm the validity of the proposed approach. The complete modem is being integrated in a 0.8 /spl mu/m BiCMOS, SOI, rad-hard technology.