H. D. B. Gottlob

Interface Defects in HfO2, LaSiOx, and Gd2O3 High-k/Metal-Gate Structures on Silicon

In this work, we present experimental results examining the energy distribution of the relatively high (> 1 X 10(11) cm(-2)) electrically active interface defects which are commonly observed in high-dielectric-constant (high-k) metal-insulator-silicon systems during high-k process development. This paper extends previous studies on the Si(100)/SiOx/HfO2 system to include a comparative analysis of the density and energy distribution of interface defects for HfO2, lanthanum silicate (LaSiOx), and Gd2O3 thin films on (100) orientation silicon formed by a range of deposition techniques. The analysis of the interface defect density across the energy gap, for samples which experience no H-2/N-2 annealing following the gate stack formation, reveals a peak density (similar to 2 X 10(12) cm(-2) eV(-1) to similar to 1 X 10(13) cm(-2) eV(-1)) at 0.83-0.92 eV above the silicon valence bandedge for the HfO2, LaSiOx, and Gd2O3 thin films on Si (100). The characteristic peak in the interface state density (0.83-0.92 eV) is obtained for samples where no interface silicon oxide layer is observed from transmission electron microscopy. Analysis suggests silicon dangling bond (P-bo) centers as the common origin for the dominant interface defects for the various Si(100)/SiOx/high-k/metal gate systems. The results of forming gas (H-2/N-2) annealing over the temperature range 350-555 degrees C are presented and indicate interface state density reduction, as expected for silicon dangling bond centers. The technological relevance of the results is discussed. (c) 2007 The Electrochemical Society.

0.86-nm CET Gate Stacks With Epitaxial

In this letter, ultrathin gadolinium oxide (Gd2O3 ) high-k gate dielectrics with complementary-metal-oxide-semiconductor (CMOS)-compatible fully silicided nickel-silicide metal gate electrodes are reported for the first time. MOS capacitors with a Gd2O3 thickness of 3.1 nm yield a capacitance equivalent oxide thickness of CET=0.86 nm. The extracted dielectric constant is k=13-14. Leakage currents and equivalent oxide thicknesses of this novel gate stack meet the International Technology Roadmap for Semiconductors targets for the near term schedule and beyond

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We investigate the impact of rapid thermal anneals on structural and electrical properties of crystalline Gd2O3 layers grown on Si with different orientations. Due to additional oxygen from the annealing ambient, a structureless two-layer stack (silicon-oxide-like and silicate-like) between the silicon and the crystalline oxide will be formed. The degradation of layers can be significantly reduced by sealing the layer with a-Si prior to annealing. For the capped layers, the effective capacitance equivalent thickness increases only slightly even after a 1000 °C anneal.

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The authors report on the investigation of amorphous Gd-based silicates as high- k dielectrics. Two different stacks of amorphous gadolinium oxide (Gd2 O3) and silicon oxide (Si O2) on silicon substrates are compared after annealing at temperatures up to 1000 °C. Subsequently formed metal oxide semiconductor capacitors show a significant reduction in the capacitance equivalent thicknesses after annealing. Transmission electron microscopy, medium energy ion scattering, and x-ray diffraction analysis reveal distinct structural changes such as consumption of the Si O2 layer and formation of amorphous Gd silicate. The controlled formation of Gd silicates in this work indicates a route toward high- k dielectrics compatible with conventional, gate first complementary metal-oxide semiconductor integration schemes.

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With the employment of ultrathin, high dielectric constant gate materials in advanced semiconductor technology, the conventional capacitance-voltage measurement technique exhibits a series of anomalies. In particular, a nonsaturating increase in the accumulation capacitance with reducing measurement frequency is frequently observed, which has not been adequately explained to our knowledge. In this article, the authors provide an explanation for this anomaly and hence set a criterion for the lower bound on measurement frequency. We then present a model which allows the easy extraction of the required parameters and apply it to an experimental set of data.

Dielectrics and FUSI NiSi Metal Electrodes

The fabrication and characterization of triple-gate p-type metal-oxide semiconductor field effect transistors (p-MOSFETs) on SOI material with multiple channels is described. To demonstrate the beneficial effects of the triple-gate structure on scaling, the output and transfer characteristics of 70 nm printed gate length pMOSFETs with 22 nm MESA width are presented. The geometrical influence of triple-gate MESA width on subthreshold behavior is investigated in short- and long channel devices. The temperature dependence of subthreshold characteristics is discussed.

Stability of crystalline Gd2O3 thin films on silicon during rapid thermal annealing

In this paper, epitaxial gadolinium oxide (Gd2O3) is reviewed as a potential high-K gate dielectric, both “as deposited” by molecular beam epitaxy as well as after integration into complementary metal oxide semiconductor (CMOS) processes. The material shows promising intrinsic properties, meeting critical ITRS targets for leakage current densities even at subnanometer equivalent oxide thicknesses. These epitaxial oxides can be integrated into a CMOS platform by a “gentle” replacement gate process. While high temperature processing potentially degrades the material, a route toward thermally stable epitaxial Gd2O3 gate dielectrics is explored by carefully controlling the annealing conditions.

Gd silicate: A High-k Dielectric Compatible with High Temperature Annealing

A triple step alignment process for UV nanoimprint lithography (UV-NIL) for the fabrication of nanoscale fin field effect transistors (FinFETs) is presented. An alignment accuracy is demonstrated between two functional layers of less than 20nm (3σ). The electrical characterization of the FinFETs fabricated by a full NIL process demonstrates the potential of UV-NIL for future nanoelectronic devices.

Leakage current effects on C-V plots of high-k metal-oxide-semiconductor capacitors

Electron capture into insulator/silicon interface states is investigated for high-k dielectrics of Gd2O3 prepared by MBE and ALD, and for HfO2 prepared by reactive sputtering, by measuring the frequency dependence of MOS capacitance. The capture cross sections are found to be thermally activated and to increase steeply with the energy depth of the interface electron states. The methodology adopted is considered useful for increasing the understanding of high-k-oxide/silicon interfaces.

Subthreshold characteristics of p-type triple-gate MOSFETs

A “gate first” silicon on insulator (SOI) complementary metal oxide semiconductor process technology for direct evaluation of epitaxial gate dielectrics is described, where the gate stack is fabricated prior to any lithography or etching step. This sequence provides perfect silicon surfaces required for epitaxial growth. The inverted process flow with silicon dioxide (SiO2)/polysilicon gate stacks is demonstrated for gate lengths from 10μm down to 40nm on a fully depleted 25nm thin SOI film. The interface qualities at the front and back gates are investigated and compared to conventionally processed SOI devices. Furthermore, the subthreshold behavior is studied and the scalability of the gate first approach is proven by fully functional sub-100nm transistors. Finally, a fully functional gate first metal oxide semiconductor field effect transistor with the epitaxialhigh-k gate dielectric gadolinium oxide (Gd2O3) and titanium nitride (TiN) gate electrode is presented.