M. Sekine

Stress relaxation in dual-damascene Cu interconnects to suppress stress-induced voiding

Stress-induced voiding (SIV) was investigated for 130 nm node dual-damascene Cu interconnects. Three SIV failure modes were revealed by TEM analyses. Cumulative failure was investigated at various metal widths, via shape and via position on a metal line at 150/spl deg/C at which the maximum failure rate was observed. Stress-induced failure at narrow Cu line was also observed, which is associated with tensile stress in Cu calculated by 3D finite element method (FEM) stress analysis. Stress relaxation by dielectric structure and quenching process were demonstrated based on stress simulation, thus the resulting SIV failure was suppressed.

Self-aligned tungsten strapped source/drain and gate technology realizing the lowest sheet resistance for sub-quarter micron CMOS

This paper describes a self-aligned tungsten strapped source/drain and gate with the lowest sheet resistance for subquarter micron CMOS. Vapor HF selective etching was applied for grooved gate structure fabrication. Selective tungsten chemical vapor deposition (W-CVD) with high pressure nucleation step was applied to fabricate tungsten strapped CMOS with recessed tungsten on poly-Si gate. The sheet resistances of 0.125 /spl mu/m wide gate and 0.25 /spl mu/m wide diffusion layer were 0.9 /spl Omega/sq. and 1.8 /spl Omega/sq. for NMOS and PMOS, respectively. This is the lowest among reported values. By using this technology, 0.22 /spl mu/m tungsten strapped CMOS was successfully fabricated.<<ETX>>

Robust porous SiOCH/Cu interconnects with ultrathin sidewall protection liners

Robust porous low-k/Cu interconnects have been developed for 65-nm-node ultralarge-scale integrations (ULSIs) with 180-nm/200-nm pitched lines and 100-nm diameter vias in a single damascene architecture. A porous plasma-enhanced chemical vapor deposition (PECVD)-SiOCH film (k=2.6) with subnanometer pores is introduced into the intermetal dielectrics on the interlayer dielectrics of a rigid PECVD-SiOCH film (k=2.9). This porous-on-rigid hybrid SiOCH structure achieves a 35% reduction in interline capacitance per grid in the 65-nm-node interconnect compared to that in a 90-nm-node interconnect with a fully rigid SiOCH. A via resistance of 9.7 /spl Omega/ was obtained in 100-nm diameter vias. Interconnect reliability, such as electromigration, and stress-induced voiding were retained with interface modification technologies. One of the key breakthroughs was a special liner technique to maintain dielectric reliability between the narrow-pitched lines. The porous surface on the trench-etched sidewall was covered with an ultrathin plasma-polymerized benzocyclobuten liner (k=2.7), thus enhancing interline time-dependent dielectric breakdown reliability. The introduction of a porous material and the control of the sidewall are essential for 65-nm-node and beyond scaled-down ULSIs to ensure high levels of reliability.

High reliability Cu interconnection utilizing a low contamination CoWP capping layer

Copper (Cu) damascene interconnects with a cobalt tungsten phosphorus (CoWP) capping layer were developed using an alkaline-metal-free electrodes plating process without palladium (Pd) catalyst activation. The wafer contamination level after processing is consistent with requirements for present LSI fabrication lines. Within wafer CoWP deposition uniformity is high and interconnects wire resistance increases by less than 5% after deposition. Electromigration (EM) testing shows no failures after two thousand hours and stress induced voiding (SIV) testing shows no failure after three thousand hours. This EM result is a 2 order or magnitude improvement over a non CoWP process.

Feasibility study of a novel molecular-pore-stacking (MPS), SiOCH film in fully-scale-down, 45nm-node Cu damascene interconnects

Molecular-pore-stacking (MPS), SiOCH films (k=2.4) are integrated in 45nm-node Cu interconnects with 140nm-pitched lines and 70nm-vias, and the feasibility is confirmed. The MPS film, which is deposited by plasma-polymerization of robust ring-type siloxane molecules, has the self-organized, porous structure with reinforcing the mechanical properties. The low permittivity is sustained in the 140nm-pitched lines by oxidation-damage-free etching, and the inter-line dielectric reliability is confirmed along with the BCB pore-seal technique, estimating 15.9% reduction in the 70nm-spaced, line capacitance refer to that of the 65nm-node SDIs. The MPS/Cu interconnect is one of the strong candidates for 45nm-node ULSI devices.

Deep Subhalf‐Micron Contact Filling Technology Using Control Etching and Collimated Ti Sputtering Techniques

We have developed a novel technology for a 0.4 μm contact with lower contact resistance using blanket W-CVD as the interconnect material. Collimated Ti sputtering followed by rapid thermal nitridation (RTN) was applied as the barrier layer for blanket W-CVD. We also developed a special chemical dry etching technique to remove the damaged Si layer caused by window etching. This damaged layer can degrade the reaction at the Ti/Si interface and causes a higher contact resistance. A mechanism is proposed to explain the contact degradation. Combined with collimated sputtering, low contact resistance for 0.4 μm p + Si contact with an aspect ratio of four was achieved and a resistivity of 1.3×10 -7 Ω-cm 2 was realized. This novel technology can be readily used to manufacture 0.25 micron ULSI devices such as 256 Mbit DRAM

Plasma Co-polymerization Technology with Molecular-level Structure Tightening in "In-situ" SiOCH Stacks for 32nm-node Cu Interconnects

A novel plasma co-polymerization technology, using flexibly-mixed molecular gas of chain-type vinyl-siloxane and 6-membered ring-type one, has been developed for new seamless low-k SiOCH stacks (SEALS). An ultimate high-modulus silica-amorphous-carbon-composite(SACC)-SiOCH film with 24.8GPa was realized by 100%-injection of the chain-type siloxane, adapting to the hard-mask on molecular-pore-stack (MPS) SiOCH film (k=2.45, 3.0GPa) from 100%-injection of the ring-type siloxane. For the via-dielectrics was utilized a new co-polymerized (CP) SiOCH film (k=2.8, 12.6GPa) from these gas mixture to enhance the mechanical strength. The in-situ sequential deposition of three kinds of films without air-break accomplished excellent adhesion, high quality interface and low O2 ashing damage. The fully-scaled-down, 32nm-node Cu interconnects achieved 83fF/mm (single-load) in 100nm-pitched Cu lines with the new co-polymerized SEALS

Low contact resistance metallization for gigabit scale DRAM's using fully-dry cleaning by Ar/H/sub 2/ ECR plasma

A fully-dry cleaning technique with Ar/H/sub 2/ Electron Cyclotron Resonance (ECR) plasma was developed as a low contact resistance metallization technology for gigabit scale DRAM contacts. By combining with ECR TiN/Ti-CVD, extremely low contact resistances of 296 /spl Omega/ and 350 /spl Omega/ for 0.3-/spl mu/m contact diameter with aspect ratio of 7 were realized on n/sup +/ and p/sup +/ diffusion layers, respectively. No leakage current was observed. By using this technology, a DRAM ULSI, which was planarized by Chemical Mechanical Polishing (CMP) and had deep contact holes with aspect ratio of 6, was successfully demonstrated.

A metallurgical prescription for electromigration (EM) reliability improvment in scaled-down, Cu dual damascene interconnects

Electromigration (EM)-derived, void-nucleation and its growth have been investigated in 65-nm node, dual damascene interconnects (DDIs), and the effects of impurity-doping as well as adhesion-strength to SiCN-capping layer (CAP) are discussed regarding the EM-reliability improvement. It is found that reductive surface-treatment of Cu line improves the adhesion to the SiCN-CAP, elongating the incubation time of voiding at the via-bottom. The Al-doping is effective in suppressions both of the void nucleation and the growth, or the drift velocity. Consequently, the Al-doped, dilute Cu-alloy with the strong interface of the Cu/CAP improves the EM lifetime by 50 times refer to that of the conventional pure-Cu. Blocking all migration paths in Cu DDIs is essential for the EM-reliability improvement in 65nm-node LSIs and beyond

A Novel Resistivity Measurement Technique for Scaled-down Cu Interconnects Implemented to Reliability-focused Automobile Applications

A novel resistivity measurement technique has been proposed for scaled-down Cu interconnects viewing the high-reliability automobile applications. This technique enables to detect the interconnect resistivity dependence on impurity concentration, free from dimension dependence. Using this technique, we investigated impacts of impurity concentration on three types of Cu interconnects: 1) CoWP cap; 2) PECVD self-aligned barrier (PSAB); and 3) CuAl interconnects and clarified the tradeoffs between resistivity and reliability. We have found that CoWP cap shows not only high-reliability but also an outstanding efficiency in suppression of resistance increase due to impurity-induced scattering, indicating that it is the most viable candidate for automobile applications in 32nm generation and beyond