Tsuneo Takeuchi

Chemical Structure Effects of Ring-Type Siloxane Precursors on Properties of Plasma-Polymerized Porous SiOCH Films

Physical and chemical properties of plasma-polymerized SiOCH films were investigated using ring-type siloxane monomers with several kinds of side-chain chemicals, and a design principle of the material and plasma-process was derived to obtain a porous SiOCH film of k < 2.5 with sub-nanometer-scaled porous structure framed by the original ring siloxane backbone. Here, the backbone siloxane structure is fixed as a six-membered Si-O ring of the 0.35 nmΦ, and no progen gas and no post-cure-process were utilized. It was found that unsaturated hydrocarbon side chains such as vinyl increase the deposition rate, and the original monomer structure tends to be kept, reducing the dielectric constant with the porous structure. Large alkyl groups increase the hydrocarbon content in the film as well as the deposition rate. The low radio-frequency power plasma with high precursor concentration also helps the original chemical structure to be preserved. The best solution is to use the ring-type siloxane with both of the vinyl (unsaturated hydrocarbon) and the large alkyl (saturated hydrocarbon) under the low-power plasma condition with the high partial pressure of the precursor. The plasma-polymerized porous SiOCH film is a strong candidate for the low-k film in scale-down 45/32 nm node ultralarge-scaled integrated interconnects featured by the simple and low-cost fabrication processes.

Mechanical Property Control of Low-

The dielectric constant dependence of the mechanical strength and the adhesion strength is investigated using porosity-controlled low-k films, and a material parameter is clarified to suppress the chemical mechanical polishing (CMP)-related defects in Cu damascene interconnects. Mechanical strengths such as the modulus and hardness of low-k films decreased as the dielectric constant decreased. Adhesion energy between the low-k films and an upper hard-mask layer (HM) of PECVD-SiO2 strongly depends on the dielectric constant of low-k films, while adhesion energy between the low-k films and a lower etch stop layer (ES) of SiCN shows weak dependence. It was found that the adhesion energy between the upper SiO2 and the low-k film is a critical mechanical parameter for diminishing the CMP-related defects. Introducing a porous low-k film, methylsilsesquiazane (k=2.64), with high adhesion to the HM-SiO2, we successfully fabricated single damascene copper interconnects within an acceptable limit of CMP-related defects.

k

High performance Cu dual-damascene (DD) interconnects without process-induced damages are developed in porous SiOCH stacks with the effective dielectric constant (keff) of 2.95, in which a carbon (C)-rich molecular-pore-stacking (MPS) SiOCH film (k = 2.5) is stacked directly on an oxygen (O)-rich porous SiOCH (k = 2.7) film. The novel etch-stopperless structure is obtained by comprehensive chemistry design of C/O ratios in the SiOCH stack and the etching plasma of an Ar/N2 /CF4 /O2 gas mixture technique. Large hydrocarbons attached to hexagonal silica backbones in the MPS-SiOCH prevent the Si-CHx bonds from oxidation during O2-plasma ashing, suppressing the C-de- pleted damage area at the DD sidewall. Combining multiresist mask process with immersion ArF photolithography, strictly controlled Cu DD interconnects with 180-nm pitched lines and 65-nm-diameter vias are obtained successfully, ready for the 300-mm fabrication.

Dielectrics for Diminishing Chemical Mechanical Polishing (CMP)-Related Defects in Cu-Damascene Interconnects

Impact of barrier metal sputtering on physical and chemical damages in the low-k SiOCH films is investigated. In RF sputtering system, the potential drop across the anode sheath accelerates the ion in the plasma toward the wafer surface, inducing damages in the low-k SiOCH dielectrics. High DC bias on the target reduces the anode sheath voltage to suppress the process-induced damage in the SiOCH films. For conventional rigid and porous SiOCH films with methyl (–CH3) additives, the accelerated ions break the Si–CH3 bond, pushing up the dielectric constants. A new type of SiOCH film such as a molecular-pore-stacking (MPS) SiOCH, which is consisted of hexagonal silica ring with a large amount of hydrocarbon groups surrounding the core silica structure, exhibits high endurance to the sputtering-induced damages. The long side-chains of the hydrocarbon prevent the direct ion bonberdment to the core Si–CH3 bonds by sacrificing the C–C bond in the chains, keeping the low dielectric constant in the MPS SiOCH.

Comprehensive Chemistry Designs in Porous SiOCH Film Stacks and Plasma Etching Gases for Damageless Cu Interconnects in Advanced ULSI Devices

We have investigated Pb(Zr,Ti)O/sub 3/ (PZT) film composition suitable for highly reliable ferroelectric RAM (FeRAM) application. To obtain a wide operational margin for 2T/2C (two transistors and two capacitors) FeRAMs, the PZT film capacitor is needed to have a low coercive voltage (V/sub c/) and a high dielectric constant on the polarization switching (/spl epsiv//sub S/) and a low dielectric constant on the nonswitching (/spl epsiv//sub N/), or essentially a large /spl epsiv//sub S///spl epsiv//sub N/ ratio. Concerning the B-site composition in the perovskite structure, it is found that lowering the Zr/Ti ratio from 47/53 to Ti-richer ones increases the ratio of /spl epsiv//sub S///spl epsiv//sub N/ as a positive effect on the wide operational margin, but increased V/sub c/ as a negative effect. Taking the balance of these factors into consideration, it is concluded that an optimum composition, such as Zr/Ti=30/70, provides the maximum operational margin. The A-site composition, on the other hand, affects the long-term reliability of a PZT capacitor. The endurance to the fatigue and imprint are enhanced by reduction of the Pb-excess and dope of La in the A-site. A La-doped PZT (Zr/Ti =30/70) capacitor is successfully integrated to the 8 kbit FeRAM macro with double-layer Al wiring to confirm the feasibility of this capacitor.

Impact of Barrier Metal Sputtering on Physical and Chemical Damages in Low-k SiOCH Films with Various Hydrocarbon Content

Robust porous low-k/Cu interconnects have been developed for 65-nm-node ultralarge-scale integrations (ULSIs) with 180-nm/200-nm pitched lines and 100-nm diameter vias in a single damascene architecture. A porous plasma-enhanced chemical vapor deposition (PECVD)-SiOCH film (k=2.6) with subnanometer pores is introduced into the intermetal dielectrics on the interlayer dielectrics of a rigid PECVD-SiOCH film (k=2.9). This porous-on-rigid hybrid SiOCH structure achieves a 35% reduction in interline capacitance per grid in the 65-nm-node interconnect compared to that in a 90-nm-node interconnect with a fully rigid SiOCH. A via resistance of 9.7 /spl Omega/ was obtained in 100-nm diameter vias. Interconnect reliability, such as electromigration, and stress-induced voiding were retained with interface modification technologies. One of the key breakthroughs was a special liner technique to maintain dielectric reliability between the narrow-pitched lines. The porous surface on the trench-etched sidewall was covered with an ultrathin plasma-polymerized benzocyclobuten liner (k=2.7), thus enhancing interline time-dependent dielectric breakdown reliability. The introduction of a porous material and the control of the sidewall are essential for 65-nm-node and beyond scaled-down ULSIs to ensure high levels of reliability.

Compositional design of Pb(Zr, Ti)O/sub 3/ for highly reliable ferroelectric memories

A feasibility study was done for 45-nm-node Cu interconnects using a novel molecular-pore-stacking (MPS) SiOCH film (k = 2.45), taking electron scattering in the scaled-down Cu lines into consideration. The as-deposited MPS SiOCH film, formed by plasma polymerization of a robust six-member-ring (hexagonal) siloxane with large steric-hindered hydrocarbon side chains, has self-organized subnanometer pores. An oxidation-damage-free dual-hard-mask etching process, along with a benzocylobuten liner technique, preserved the low permittivity of the MPS film in the Cu lines, with excellent interline dielectric reliability. The line aspect ratio was also balanced to decrease not only the interconnect parasitic capacitance but also the Cu line resistivity, which is increased by the electron scattering in the narrow lines. By combining the above etching process and the line-aspect control, the feasibility of the MPS SiOCH film was confirmed with outstanding performance and excellent reliability for the 45-nm-node ultralarge scale integrations

Robust porous SiOCH/Cu interconnects with ultrathin sidewall protection liners

Chip packaging technology with a circuit-under-pad (CUP) structure is developed for porous SiOCH (k=2.55)/Cu dual-damascene interconnects. Wire bonding damage is mainly improved by the pad structure. For the molding process, it is important to decrease the coefficient of thermal expansion (CTE) of the molding compounds. Combining the stress controls in these packaging processes with the contrived low-k deposition, high performance 65 nm-node ULSI chips are furnished in low-cost QFP with conventional wire bonding.

Feasibility Study of 45-nm-Node Scaled-Down Cu Interconnects With Molecular-Pore-Stacking (MPS) SiOCH Films

A highly reliable, 65 nm-node Cu interconnect technology has been developed with 180 nm/200 nm-pitched lines connected through /spl phi/100 nm-vias. A porous SiOCH film (k=2.5) with sub-nanometer pores is introduced for the inter-metal dielectrics (IMD) on a non-porous, rigid SiOCH film (k=2.9) for the via-infra-line dielectrics (via-ILD). A key breakthrough is a special pore-seal technique, in which the trench-etched surface of the porous SiOCH is covered with an ultra-thin, low-k organic silica film (k=2.7), thus improving the line-to-line TDDB (time dependent dielectric breakdown) reliability of the narrow-pitched Cu lines. The fully-scaled-down, 65 nm-node Cu interconnects with the porous-on-rigid SiOCH hybrid structure achieve excellent performance and reliability.

Comprehensive process design for low-cost chip packaging with circuit-under-pad (CUP) structure in porous-SiOCH film

Molecular-pore-stacking (MPS), SiOCH films (k=2.4) are integrated in 45nm-node Cu interconnects with 140nm-pitched lines and 70nm-vias, and the feasibility is confirmed. The MPS film, which is deposited by plasma-polymerization of robust ring-type siloxane molecules, has the self-organized, porous structure with reinforcing the mechanical properties. The low permittivity is sustained in the 140nm-pitched lines by oxidation-damage-free etching, and the inter-line dielectric reliability is confirmed along with the BCB pore-seal technique, estimating 15.9% reduction in the 70nm-spaced, line capacitance refer to that of the 65nm-node SDIs. The MPS/Cu interconnect is one of the strong candidates for 45nm-node ULSI devices.