N. Furutake

A novel vertical current limiter fabricated with a deep trench forming technology for highly reliable field emitter arrays

We have developed highly reliable field emitter arrays with a novel vertical current limiter fabricated with a deep trench forming technology. The vertical current limiter has a local current-control function that automatically prevents fatal arc failure, and it has low resistance when used in the normal operation of a field emitter array. It has demonstrated a breakdown voltage as high as 120 V and a negligible increase in operation voltage, i.e., Vg of 70 V at 1 /spl mu/A/tip with an emitter cone density of more than 5/spl times/10/sup 7/ emitters/cm/sup 2/.

Highly-Reliable Low-Resistance Cu Interconnects with PVD-Ru/Ti Barrier Metal toward Automotive LSIs

Highly-reliable Cu interconnects with Ru/Ti barrier metal have been developed, in which Ti is diffused into the Ru-layer to establish a Cu-diffusion barrier. The PVD-Ru/Ti barrier metal with preferable crystal-orientation to Cu texture achieves the low line resistance. The Ti-doping in the Cu grain boundary just under the via improves the Cu-via reliabilities, besides keeping the Cu line resistance low. The Cu line with the Ru/Ti barrier metal is a strong candidate for automotive LSIs in future, requiring high performance and ultra-high reliability.

Suppression of stress induced open failures between via and Cu wide line by inserting Ti layer under Ta/TaN barrier

We verified the effect of Ti layer insertion on stress induced void formation in wide Cu lines where voids were formed under via. In order to improve adhesion property between via and underlying Cu, PVD-Ti was inserted under Ta/TaN barrier. When nominal 30 nm thick PVD-Ti layer was inserted (Ti thickness at via bottom was about 8 nm), the failure was sufficiently suppressed without degrading the electromigration resistance. In addition, the via resistance was reduced by 25% compared with conventional Ta/TaN barrier structure, while the Cu metal resistivity was unchanged by the Ti insertion.

Dual hard mask process for low-k porous organosilica dielectric in copper dual damascene interconnect fabrication

Using a low-k porous organosilisesqueoxane film, ALCAP/sup TM/-S with k=2.1, dual hard mask (DHM) process is proposed for Cu dual damascene interconnect (DDI) formation. The porous organosilica film has very high etching rate relative to those of the hard mask (HM) and/or etch-stop materials. SiO/sub 2//SiC is one of the best combinations for the DHM, in which the lower hard mask of SiC remained after metal CMP and protects the porous film from the via-etching damage in misalignnent region between the via-hole and the buried Cu-line. Applying in-situ resist-ashing with N/sub 2//H/sub 2/ gas, 0.4 /spl mu/m-pitched dual damascene structure is successfully fabricated. Increment of the dielectric constant is suppressed within 5% (k=2.2) after the Cu-interconnect fabrication, confirming that the DHM low-damage process is applicable for the Cu DDI fabrication in ultra low-k, porous organosilica systems.

A 65nm-node, Cu interconnect technology using porous SiOCH film (k=2.5) covered with ultra-thin, low-k pore seal (k=2.7)

A highly reliable, 65 nm-node Cu interconnect technology has been developed with 180 nm/200 nm-pitched lines connected through /spl phi/100 nm-vias. A porous SiOCH film (k=2.5) with sub-nanometer pores is introduced for the inter-metal dielectrics (IMD) on a non-porous, rigid SiOCH film (k=2.9) for the via-infra-line dielectrics (via-ILD). A key breakthrough is a special pore-seal technique, in which the trench-etched surface of the porous SiOCH is covered with an ultra-thin, low-k organic silica film (k=2.7), thus improving the line-to-line TDDB (time dependent dielectric breakdown) reliability of the narrow-pitched Cu lines. The fully-scaled-down, 65 nm-node Cu interconnects with the porous-on-rigid SiOCH hybrid structure achieve excellent performance and reliability.

Barrier-metal-free (BMF), Cu dual-damascene interconnects with Cu-epi-contacts buried in anti-diffusive, low-k organic film

Barrier-metal-free (BMF) Cu dual-damascene interconnects (DDI) are fabricated in the plasma-polymerized, divinyl siloxane bis-benzocyclobutene (p-BCB: k=2.6) polymer film, which is characterised by anti-diffusive characteristics for the Cu. The BMF-structure has inter-line leakage current as low as that of a conventional barrier-inserted structure and is estimated to retain the high insulating properties for over 10 years under 1 MV/cm stress. The BMF-structure also derives Cu-epi-contacts, reducing the via-resistance to 50% of that of the conventional Cu/barrier/Cu contacts. The effective dielectric constant was k/sub eff/=3.1, including very thin SiN etch-stop-layers, accomplishing 20% faster CMOS device operation compared to that of the conventional Cu-DDI in the SiO/sub 2/ with Ta-TaN barriers. The BMF Cu-DDIs buried directly in the p-BCB film is one of the ultimate structures for high performance, 0.1 /spl mu/m-CMOS devices and beyond.

Fully large-scale integration-process-compatible Si field emitter technology with high controllability of emitter height and sharpness

We developed a fully large-scale integration (LSI)-process-compatible technology with excellent control of emitter shape for the first time. The fabricated emitter tip configuration has two-step-cone shape whose upper and lower cone configurations are controllable independently. While the upper parts determine the emitter tip sharpness and the apex angle, the lower parts determine the emitter height by utilizing two-step thermal oxidation for emitter tip sharpening in addition to anisotropic reactive ion etching for the emitter height control. The stable and uniform thermal oxidation for sharpening emitters produces excellent uniformity, and the process, without liftoff, is matched with Si LSI technology completely. The obtained 1944 tip emitter with 800 nm gate diameter showed low threshold voltage of 35 V.

Feasibility study of a novel molecular-pore-stacking (MPS), SiOCH film in fully-scale-down, 45nm-node Cu damascene interconnects

Molecular-pore-stacking (MPS), SiOCH films (k=2.4) are integrated in 45nm-node Cu interconnects with 140nm-pitched lines and 70nm-vias, and the feasibility is confirmed. The MPS film, which is deposited by plasma-polymerization of robust ring-type siloxane molecules, has the self-organized, porous structure with reinforcing the mechanical properties. The low permittivity is sustained in the 140nm-pitched lines by oxidation-damage-free etching, and the inter-line dielectric reliability is confirmed along with the BCB pore-seal technique, estimating 15.9% reduction in the 70nm-spaced, line capacitance refer to that of the 65nm-node SDIs. The MPS/Cu interconnect is one of the strong candidates for 45nm-node ULSI devices.

A novel cylinder-type MIM capacitor in porous low-k film (CAPL) for embedded DRAM with advanced CMOS logics

A novel cylinder-type metal-insulator-metal (MIM) capacitor in porous low-k film (CAPL) is proposed for embedded DRAMs (eDRAMs). The CAPL removes long bypass-contacts (BCT) with high resistance, which have been used to connect transistors with Cu interconnects by way of the MIM capacitor layer. A key technical challenge for the CAPL integration is control of pore structure in the low-k film to avoid metal contamination during the gas-phase deposition of the MIM electrode (BE) on the porous low-k film. A molecular-pore-stack (MPS) SiOCH film (k=2.5) with very small pores (0.4 nm-diameter) is found to be the best candidate for the CAPL structure, applicable to eDRAM with high performance logics for 28 nm-node and beyond.

45nm-node Interconnects with Porous SiOCH-Stacks, Tolerant of Low-Cost Packaging Applications

The 45 nm-node interconnect with porous SiOCH-stacks of keff=2.9 is confirmed to have the practical reliability in PGBA and QFP. Adhesion strength of the via-ILD to the lower SiCN capping layer significantly impacts on the wire-bond reliability, but spreading the contact area of the bonding-wire within the fine-pitched bonding-pad suppresses the bonding failures in the low-k stack structures, irrespective of additional process of low-k curing or not. No failure was detected during reliability tests in PBGA package as well as QFP, confirming the practicality of the low keff interconnects for 45 nm-node ULSIs.