Shinobu Saito

Mechanical Property Control of Low-

The dielectric constant dependence of the mechanical strength and the adhesion strength is investigated using porosity-controlled low-k films, and a material parameter is clarified to suppress the chemical mechanical polishing (CMP)-related defects in Cu damascene interconnects. Mechanical strengths such as the modulus and hardness of low-k films decreased as the dielectric constant decreased. Adhesion energy between the low-k films and an upper hard-mask layer (HM) of PECVD-SiO2 strongly depends on the dielectric constant of low-k films, while adhesion energy between the low-k films and a lower etch stop layer (ES) of SiCN shows weak dependence. It was found that the adhesion energy between the upper SiO2 and the low-k film is a critical mechanical parameter for diminishing the CMP-related defects. Introducing a porous low-k film, methylsilsesquiazane (k=2.64), with high adhesion to the HM-SiO2, we successfully fabricated single damascene copper interconnects within an acceptable limit of CMP-related defects.

k

High performance Cu dual-damascene (DD) interconnects without process-induced damages are developed in porous SiOCH stacks with the effective dielectric constant (keff) of 2.95, in which a carbon (C)-rich molecular-pore-stacking (MPS) SiOCH film (k = 2.5) is stacked directly on an oxygen (O)-rich porous SiOCH (k = 2.7) film. The novel etch-stopperless structure is obtained by comprehensive chemistry design of C/O ratios in the SiOCH stack and the etching plasma of an Ar/N2 /CF4 /O2 gas mixture technique. Large hydrocarbons attached to hexagonal silica backbones in the MPS-SiOCH prevent the Si-CHx bonds from oxidation during O2-plasma ashing, suppressing the C-de- pleted damage area at the DD sidewall. Combining multiresist mask process with immersion ArF photolithography, strictly controlled Cu DD interconnects with 180-nm pitched lines and 65-nm-diameter vias are obtained successfully, ready for the 300-mm fabrication.

Dielectrics for Diminishing Chemical Mechanical Polishing (CMP)-Related Defects in Cu-Damascene Interconnects

Low-damage hard-mask (HM) plasma-etching technology for porous SiOCH film (k=2.6) has been developed for robust 65-nm-node Cu dual damascene interconnects (DDIs). No damage is introduced by fluorocarbon plasma etching irrespective of whether rigid (k=2.9) or porous (k=2.6) SiOCH films are used, due to the protective CF-polymer layer deposited on the etched sidewall. The etching selectivity of the SiOCH films to the inorganic HMs is kept high by controlling the radical ratio of carbon relative to oxygen in the etching plasma gas. However, oxidation damage penetrates the films from the sidewalls due to the O2 plasma used for photoresist ashing. This damage is increased by the porous structure. As a result, we developed a via-first multi-hard-mask process for the DD structure in porous SiOCH film with no exposure to O 2-ashing plasma, and we controlled the via-taper angle by RF bias during etching. We fabricated robust Cu DDIs with tapered vias in porous SiOCH film that can be applied to 65-nm-node ULSIs and beyond

Comprehensive Chemistry Designs in Porous SiOCH Film Stacks and Plasma Etching Gases for Damageless Cu Interconnects in Advanced ULSI Devices

Robust porous low-k/Cu interconnects have been developed for 65-nm-node ultralarge-scale integrations (ULSIs) with 180-nm/200-nm pitched lines and 100-nm diameter vias in a single damascene architecture. A porous plasma-enhanced chemical vapor deposition (PECVD)-SiOCH film (k=2.6) with subnanometer pores is introduced into the intermetal dielectrics on the interlayer dielectrics of a rigid PECVD-SiOCH film (k=2.9). This porous-on-rigid hybrid SiOCH structure achieves a 35% reduction in interline capacitance per grid in the 65-nm-node interconnect compared to that in a 90-nm-node interconnect with a fully rigid SiOCH. A via resistance of 9.7 /spl Omega/ was obtained in 100-nm diameter vias. Interconnect reliability, such as electromigration, and stress-induced voiding were retained with interface modification technologies. One of the key breakthroughs was a special liner technique to maintain dielectric reliability between the narrow-pitched lines. The porous surface on the trench-etched sidewall was covered with an ultrathin plasma-polymerized benzocyclobuten liner (k=2.7), thus enhancing interline time-dependent dielectric breakdown reliability. The introduction of a porous material and the control of the sidewall are essential for 65-nm-node and beyond scaled-down ULSIs to ensure high levels of reliability.

Robust Cu Dual Damascene Interconnects With Porous SiOCH Films Fabricated by Low-Damage Multi-Hard-Mask Etching Technology

Stress-induced voiding (SIV) is a serious problem in Cu dual-damascene interconnects (DDIs). The stress gradient under vias is the driving force of vacancy diffusion and void generation, therefore stress control in Cu-DDI is an important factor for suppressing SIV. In this study, the stress effect of upper Cu film on SIV in lower Cu lines is investigated, and the stress distribution in Cu-DDI is analyzed by finite element analysis. It is found that SIV in the lower Cu lines is strongly affected not only by the width of lower lines but also by the metallurgical properties of the Cu film in upper metals. Suppression of tensile stress in the via of the upper Cu film decreases the stress gradient in the lower line around the via, and eventually, the driving force of vacancy diffusion to the via bottom. Control of the metallurgical properties to suppress Cu creep during annealing is a key factor for decreasing SIV in lower Cu lines. High-temperature deposition of Cu film with a small coefficient of thermal expansion (CTE) is a solution to suppressing SIV failure in Cu-DDIs.

Robust porous SiOCH/Cu interconnects with ultrathin sidewall protection liners

A low oxygen content (LOC) CuAl alloy with no barrier metal (Ta) oxidation was obtained using an oxygen absorption process based on metallurgical thermodynamic principles. LOC CuAl dual damascene interconnects (DDIs) were successfully implemented into 45-nm-node LSIs with 140-nm-pitched lines and 70-nm-diameter (phi) vias. An oxygen absorber of very thin Al film, which was deposited on an electrochemically deposited (ECD) Cu film, captured the oxygen atoms in the ECD Cu due to its larger negative change in the standard Gibbs-free energy of oxidation than in the Cu and the barrier (Ta), preventing the Ta barrier from oxidizing during high-temperature annealing. The high-quality Cu/barrier interface in the LOC CuAl DDIs remarkably improved the via reliability against stress-induced voiding and electromigration. No reliability degradation of the 70-nm-phi vias was observed in the 45-nm-node LOC CuAl DDIs, while keeping the scalability from the 65-nm-node generation.

Effects of the Metallurgical Properties of Upper Cu Film on Stress-Induced Voiding (SIV) in Cu Dual-Damascene Interconnects

Hybrid-type, Cu dual damascene interconnects (DDI) are fabricated in a porous organosilica film (k = 2.1) inserted between low-k films of hard-mask (HM) and etch-stop (ES) layers. Plasma-polymerized, divinyl siloxane bis-benzocyclobutene (p-BCB, k = 2.7) film, instead of SiCN film (k > 4), is selected for these HM and ES layers due to the low k-value as well as the high etch-stop property to the porous film. The line capacitance in the hybrid-type, Cu-DDI with BCB-HM and BCB-ES layers decreases 20% compared with that of the Cu-DDI with SiO/sub 2/-HM and SiCN-ES layers, achieving the effective dielectric constant (k/sub eff/) of 2.6. This new interconnect structure is a strong candidate for the 70 nm-node ULSIs.

Robust Low Oxygen Content Cu Alloy for Scaled-Down ULSI Interconnects Based on Metallurgical Thermodynamic Principles

A novel cylinder-type metal-insulator-metal (MIM) capacitor in porous low-k film (CAPL) is proposed for embedded DRAMs (eDRAMs). The CAPL removes long bypass-contacts (BCT) with high resistance, which have been used to connect transistors with Cu interconnects by way of the MIM capacitor layer. A key technical challenge for the CAPL integration is control of pore structure in the low-k film to avoid metal contamination during the gas-phase deposition of the MIM electrode (BE) on the porous low-k film. A molecular-pore-stack (MPS) SiOCH film (k=2.5) with very small pores (0.4 nm-diameter) is found to be the best candidate for the CAPL structure, applicable to eDRAM with high performance logics for 28 nm-node and beyond.

Cu dual damascene interconnects in porous organosilica film with organic hard-mask and etch-stop layers for 70 nm-node ULSIs

The impact of porous low-k films on circuit performance in GHz operation was investigated using high-speed circuits in 65 nm complementary metal oxide semiconductor (CMOS) LSI with 11-layered Cu dual damascene interconnects (DDIs). By introducing new non-porogen-type porous films, such as molecular-pore-stacking (MPS) SiOCH films, local low-k/Cu structures (M2–M5) with effective dielectric constants (Keff) of 3.1 and 2.9 were fabricated, and their circuit performances were compared to those with conventional local interconnects with Keff=3.4. The interline capacitance (Cint), measured using an LCR meter at ~100 kHz, was reduced by 12% from Keff=3.4 to 2.9. NAND-type ring oscillators (ROSCs), which were designed to have ~1.5 GHz oscillation, also achieved 12 and 10% reductions in signal delay and power consumption, respectively. A 2 GHz static random access memory (SRAM) with Keff=2.9 provides a 4% reduction in bit-line capacitance (M2), resulting in a 6% decrease in Vddmin, or eventually widening the SRAM operation margin. The porous low-k impact on GHz operation is demonstrated for the first time.

A novel cylinder-type MIM capacitor in porous low-k film (CAPL) for embedded DRAM with advanced CMOS logics

The 45 nm-node interconnect with porous SiOCH-stacks of keff=2.9 is confirmed to have the practical reliability in PGBA and QFP. Adhesion strength of the via-ILD to the lower SiCN capping layer significantly impacts on the wire-bond reliability, but spreading the contact area of the bonding-wire within the fine-pitched bonding-pad suppresses the bonding failures in the low-k stack structures, irrespective of additional process of low-k curing or not. No failure was detected during reliability tests in PBGA package as well as QFP, confirming the practicality of the low keff interconnects for 45 nm-node ULSIs.