Naoya Inoue

Highly reliable BEOL-transistor with oxygen-controlled InGaZnO and Gate/Drain offset design for high/low voltage bridging I/O operations

Reliability of BEOL-transistors with a wide-gap oxide semiconductor InGaZnO (IGZO) film, integrated on LSI Cu-interconnects, is intensively discussed in terms of application to on-chip bridging I/Os between low and high voltage interactive operations (Fig. 1). Oxygen control in the thin IGZO film was found to be important to stabilize the device characteristics. A conventional IGZO tends to contain deep-level donor-states, which cause temperature and bias instabilities. The oxygen control in IGZO reduces these deep donor-states to improve operation instability. A gate/drain offset structure effectively suppresses the hot-carrier generation, resulting in a stable operation at high Vd bias condition (∼20V). The oxygen-controlled IGZO and gate/drain offset structure are important for making the BEOL-transistors applicable to high/low voltage I/Os bridging.

UV cure impact on robust low-k with sub-nm pores and high carbon content for high performance Cu/low-k BEOL modules

UV cure on robust low-k with sub-nm pore and high carbon content (R-ELK=Robust ELK) was studied to enhance the modulus of the film. UV cure helps to create Si-CH2-Si bridging bond, which plays a role to enhance the modulus. UV cure does not affect the advantage of low PID (plasma-induced damage) and it was confirmed by Cint (interconnect capacitance) measurement for 80 nm pitch interconnect. Besides, UV cured R-ELK demonstrated high TDDB and EM reliability, with lifetime similar to the mature ULK baseline. High TDDB reliability with further dimensional scaling was also confirmed for the test structure with 20 nm spacing.

Robust low-k film with sub-nm pores and high carbon content for highly reliable Cu/low-k BEOL modules

Critical parameters of low-k films were defined to keep capacitance benefit and TDDB reliability in the scaling BEOL module, according to various analyses. In order to meet the criteria of high carbon content, low porosity with small pores, and high adhesion strength with less adhesion layer, precursor and process were designed for the SiOCH with k~2.5. The benefits in integration and reliability from the newly developed robust low-k film were verified through the trench-first integration of 80 nm-pitch BEOL modules.

Effects of metal-cap coverage on electro-migration (EM) tolerance for scaled-down Cu interconnects

Ultra-high electro-migration tolerant Cu interconnect was achieved by full-coverage metal-cap combined with a porous low-k film having a closed-pore structure such as a molecular-pore-stack (MPS) SiOCH film (k∼2.5). We found that the key feature for the high reliability is “full coverage” of the Cu surface with Co-based metal-cap without Co-penetration into the porous film. The full-coverage metal cap on the pure Cu interconnect improved EM lifetime drastically by “6000 times”, while a partial-coverage metal cap limits the improvement only by 10 times. The interconnect resistance was kept low within +3.2% increment from the pure Cu one, which is far less than that of a Cu-alloy interconnect. Perfect block of the Cu surface-diffusion by the metal cap takes us into another dimension regarding the Cu interconnect reliability, desirable for deeply scaled-down SoCs below 20nm-nodes and/or MCUs under very high temperature environments.

Enhanced drivability of high-V bd dual-oxide-based complementary BEOL-FETs for compact on-chip pre-driver applications

Enhanced current drivability of BEOL-process-compatible dual-oxide complementary BEOL-FETs on LSI-interconnects (Fig. 1) with just two additional masks to the state-of-the-art BEOL process is demonstrated, aiming at high-Vbd pre-driver operation. We have developed processes so that IGZO-based NFETs have lower ARon as compared to currently available Si power devices (Fig. 6). We also developed new SnO processes, realizing a 30× Ion boost for PFETs. Dual oxide semiconductor channels are integrated to form BEOL-CMOS inverters with stable and sharp cut-off characteristics (Figs. 8 and 9) for lower power operation, leading to a successful operation of an integrated 6T-SRAM cell (Fig. 11). Pre-driver capability of NFET inverters is demonstrated with MCU-controlled operation of brushless DC (BLDC) motors (Fig. 12). This technology is a strong candidate to realize high-Vbd pre-drivers and low-power logic on BEOL, which gives standard LSIs a special add-on function for smart society applications.

Control of plasma polymerization reaction for the 2 nd generation molecular_pore_stack (MPS) SiOCH film with high deposition rate

To reducing BEOL fabrication cost for 28/20nm-nodes, high-speed process of the low-k deposition is needed under limited equipment investment. By using a standard plasma-CVD equipment with no post-cure process, we have developed high speed deposition technique for a molecular_pore_stack (MPS) SiOCH film from single precursor, which has a hexagonal-silica-ring with hydrocarbon side-chains. Here, the plasma polymerization reaction of the precursors was enhanced simply by controlling the RF power and the gas chemistry with additive gas, which was dissociated itself to increase active charge flux in the plasma. The deposition rate was doubled while keeping the film properties unchanged with the sub-nanometer-size porous structure. No change in the RC performance of the Cu interconnect was observed by using the new MPS film with the high deposition rate. The mechanical properties also were preserved to keep chip-packaging-interaction tolerance.

Highly reliable molecular-pore-stacking (MPS)/Cu interconnects using novel post-etching treatment (PET) for 28 nm-node and beyond

Effects of post-etching treatment (PET) in trench patterning and re-sputtering in barrier metal sputtering on low-k/Cu interconnects were investigated for the low-k of Molecular Pore Stacking (MPS). Optimized combination of PET and re-sputtering reduces wiring capacitance by 5% due to well controlled profile, resulted from hardening effect of the exposed MPS at the trench bottom. The developed process sequence achieves 10 times loger EM lifetime and eliminates early failure mode in the TDDB test. Thus, the novel process, featuring PET and re-sputtering, contributes to highly reliability for 28 nm node CMOS and beyond.

Performance Evaluation of a Logic-IP Compatible (LIC) Embedded DRAM with Cylinder Capacitors in Low-k/Cu BEOL Layers

Introduction Embedded DRAMs (eDRAMs) are attractive for realizing high bandwidth, low latency, and low power of the memory-logic interface with small cell size [1-2]. In the conventional “capacitor over bit-line (COB)” structure, cylinder capacitors for storage nodes are located between M1 and bit-lines, and bypass-contacts need to be added to the conventional contacts for connecting CMOS transistors to M1 (Fig.1). For deep scaling beyond 40 nm technology, higher cylinder capacitors are needed to keep the node capacitance (Cs) per each cell. This may lead to significant increase of the contacts (CT) height, parasitic resistance and capacitance, or even RC-delay of the logic parts in the eDRAM circuit. We have proposed a novel concept of the logic-IP compatible (LIC) eDRAM containing cylinder capacitors in low-k/Cu BEOL layers, and confirmed feasibility of the capacitor integration with low CT heights to keep compatibility with standard CMOS logic IPs [3]. The LIC-eDRAM is categorized as a “BEOL memory,” of which memory elements are located in interconnect layers such as MRAM [4] and ReRAM [5]. In this paper, we focus on the logic delays of the LIC-eDRAM referred to those of the pure CMOS logics obtained by the circuit simulation for 28nm-node in conjunction with the actual measurement for 40nm-node test-chips.