J. Juan-Chico

Degradation Delay Model Extension to CMOS Gates

This contribution extends the Degradation Delay Model (DDM), previously developed for CMOS inverters, to simple logic gates. A gate-level approach is followed. At a first stage, all input collisions producing degradation are studied and classified. Then, an exhaustive model is proposed, which defines a set of parameters for each particular collision. This way, a full and accurate description of the degradation effect is obtained (compared to HSPICE) at the cost of storing a rather high number of parameters. To solve that, a simplified model is also proposed maintaining similar accuracy but with a reduced number of parameters and a simplified characterization process. Finally, the complexity of both models is compared.

Inertial and degradation delay model for CMOS logic gates

The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital simulation. The model combines the degradation delay model presented in previous papers with a new algorithm to handle the inertial effect, and is able to take account of the propagation and filtering of arbitrarily narrow pulses (glitches, etc.). The model clearly overcomes the limitations of conventional approaches.

Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level

Accurate estimation of switching activity is very important in digital circuits. In this paper we present a comparison between the evaluation of the switching activity calculated using logic (Verilog) and electrical (HSPICE) simulators. We also study how the variation on the delay model (min, typ, max) and parasitic effects affect the number of transitions in the circuit. Results show a variable and significant overestimation of this measurement using logic simulators even when including postlayout effects. Furthermore, we show the contribution of glitches to the overall switching activity, giving that the treatment of glitches in conventional logic simulators is the main cause of switching activity overestimation.

HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model

This paper presents HALOTIS, a novel high accuracy logic timing simulation tool, that incorporates a new simulation algorithm based on different concepts for transitions and events. This new simulation algorithm is intended for including the inertial and degradation delay models. Simulation results are very similar to those obtained by electrical simulators, and show a higher accuracy compared to conventional delay models implemented in current logic simulators.

Analysis of Metastable Operation in a CMOS Dynamic D-Latch

Nowadays, metastability is becoming a serious problemin high-performance VLSI design, mainly due to the relatively-highprobability of error when a bistable circuit operates at highfrequencies. As far as we know, there is not any work publishedthat justifies and formally characterizes metastable behaviorin dynamic latches. With current technologies, dynamic latchesare widely used in high-performance VLSI circuits, mainly dueto their lower cost and higher operation speed than static latches.In this work, we demonstrate that dynamic memory cells presentan anomalous behavior referred to as metastable operation withcharacteristics similar to those of static latches. We performa suitable generalization of metastability to the dynamic case,applying it to a CMOS dynamic D-latch. A theoretical model willbe proposed, allowing the quantification of metastability, andit will be validated through electric simulation with HSPICE.After that, we have compared the metastable behavior of the dynamiclatch with its static counterpart, obtaining results about thecharacteristic parameters of metastability and the Mean TimeBetween Failures (MTBF) for both kinds of bistable circuits.These results have allowed us to conclude that, unlike metastabilitywindows in static latches, a clearly defined input interval existswhich produces an infinite resolution time. Regarding MTBF, thedynamic latch presents a very low MTBF value compared to thestatic latch. These results show that dynamic latches shouldnot be used in those circuits where the risk of asynchronismbetween clock and data signals is not negligible.

Logic-Level fast current simulation for digital CMOS circuits

Nowadays, verification of digital integrated circuit has been focused more and more from the timing and area field to current and power estimations. The main problem with this kind of verification is on the lack of precision of current estimations when working at higher levels (logic, RT, architectural levels). To solve this problem it is not only necessary to use good current models for switching activity but, also, it is necessary to calculate this switching activity with high accuracy. In this paper we present an alternative to estimate current consumption using logic-level simulation. To do that, we use a simple but accurate enough current model to calculate the current consumption for each signal transition, and a delay model that obtains high accuracy when it is used to measure the switching activity (the Degradation Delay Model -DDM-). In the paper we present the current model for CMOS inverter, the characterization process and the model implementation in the logic simulator HALOTIS that includes the DDM. Results show a high accuracy in the estimation of current curves when compared to HSPICE, and a potentially large improvement over conventional approaches.

Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level

This contribution presents a method to obtain current estimations at the logic level. This method uses a simple current model and a current curve generation algorithm that is implemented as an attached module to a logic simulator under development called HALOTIS. The implementation is aimed at efficiency and overall estimations, making it suitable to switching noise evaluation and current peaks localisation. Simulation results and comparison to HSPICE confirm the usefulness and efficiency of the approach.

AUTODDM: automatic characterization tool for the delay degradation model

As delay models used in logic timing simulation become more and more complex, the problem of model parameter values extraction arise as an important issue, which it is necessary to face in order to achieve a practical implementation of the model. In this way, this paper describes the characterization process associated with the previously developed delay degradation model for CMOS logic gates (DDM) and the implementation of an automatic characterization tool that automates the process and allows easy and fast model parameter extraction.

Application of internode model to global power consumption estimation in SCMOS gates

In this paper, we present a model, Internode, that unifies the gate functional behavior and the dynamic one. It is based on a FSM that represents the internal state of the gate depending on the electrical load of its internal nodes allowing to consider aspects like input collisions and internal power consumption. Also, we explain the importance of internal power consumption (such effect occurs when an input transition does not affect the output) in three different technologies (AMS 0.6 μm, AMS 0.35 μm, and UMC 130 nm). This consumption becomes more remarkable as technology advances yielding to underestimating up to 9.4% of global power consumption in the UMC 130 nm case. Finally, we show how to optimize power estimation in the SCMOS NOR-2 gate by applying Internode to modeling its consumption accurately.

Gate-level simulation of CMOS circuits using the IDDM model

Timing verification of digital CMOS circuits is a key point in the design process. In this contribution we present the extension to gates of the Inertial and Degradation Delay Model for logic timing simulation which is able to take account of the propagation of arbitrarily narrow pulses. As a result, the model is ready to be applied to the simulation and verification of complex circuits. Simulation results show an accuracy similar to HSPICE and greatly improved precision over conventional delay models.