M. von Haartman

Comprehensive study on low-frequency noise and mobility in Si and SiGe pMOSFETs with high-/spl kappa/ gate dielectrics and TiN gate

Low-frequency noise and hole mobility are studied in Si and SiGe surface channel pMOSFETs with various types of high-/spl kappa/ dielectric stacks (Al/sub 2/O/sub 3/, Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/ and Al/sub 2/O/sub 3//HfO/sub 2//Al/sub 2/O/sub 3/) and TiN as gate electrode material. Comparisons are made with poly-SiGe-gated pMOSFETs as well as poly-Si/SiO/sub 2//Si references. The choice of channel material (strained SiGe or Si), gate material (TiN or poly-SiGe), and high-/spl kappa/ material (Al/sub 2/O/sub 3/, HfO/sub 2/, HfAlO/sub x/) is discussed in terms of mobility and low-frequency noise. A TiN gate in combination with a surface SiGe channel is advantageous both for enhanced mobility and low 1/f noise. The dominant sources of carrier scattering are identified by analyzing the mobility measured at elevated temperatures. The 1/f noise is studied from subthreshold to strong inversion conditions and at different substrate biases. The mobility fluctuation noise model and the number fluctuation noise model are both used to investigate the 1/f-noise origin.

Lateral encroachment of Ni-silicides in the source/drain regions on ultrathin silicon-on-insulator

Lateral growth of Ni silicide towards the channel region of metal-oxide-semiconductor transistors (MOSFETs) fabricated on ultrathin silicon-on-insulator (SOI) is characterized using SOI wafers with a 20-nm-thick surface Si layer. With a 10-nm-thick Ni film for silicide formation, p-channel MOSFETs displaying ordinary device characteristics with silicided p+ source/drain regions were demonstrated. No lateral growth of NiSix under gate isolation spacers was found according to electron microscopy. When the Ni film was 20 nm thick, Schottky contact source/drain MOSFETs showing typical ambipolar characteristics were obtained. A severe lateral encroachment of NiSix into the channel region leading to an increased gate leakage was revealed, while no detectable voiding at the silicide front towards the Si channel was observed.

Hole mobility in ultrathin body SOI pMOSFETs with SiGe or SiGeC channels

The hole mobilities of SiGe and SiGeC channel pMOSFETs fabricated on ultrathin silicon-on-insulator substrates are investigated and compared with reference Si channel devices. The total thickness of the fully depleted Si/SiGe(C)/Si body structure is /spl sim/ 25 nm. All devices demonstrated a near ideal subthreshold behavior, and the drive current and mobility were increased with more than 60% for SiGe and SiGeC channels. When comparing SIMOX and UNIBOND substrates, no significant difference could be detected.

A novel strained Si0.7Ge0.3 surface-channel pMOSFET with an ALD TiN/Al2O3/HfAlOx/Al2O3 gate stack

Proof-of-concept pMOSFETs with a strained-Si/sub 0.7/Ge/sub 0.3/ surface-channel deposited by selective epitaxy and a TiN/Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/ gate stack grown by atomic layer chemical vapor deposition (ALD) techniques were fabricated. The Si/sub 0.7/Ge/sub 0.3/ pMOSFETs exhibited more than 30% higher current drive and peak transconductance than reference Si pMOSFETs with the same gate stack. The effective mobility for the Si reference coincided with the universal hole mobility curve for Si. The presence of a relatively low density of interface states, determined as 3.3 /spl times/ 10/sup 11/ cm/sup -2/ eV/sup -1/, yielded a subthreshold slope of 75 mV/dec. for the Si reference. For the Si/sub 0.7/Ge/sub 0.3/ pMOSFETs, these values were 1.6 /spl times/ 10/sup 12/ cm/sup -2/ eV/sup -1/ and 110 mV/dec., respectively.

Low‐frequency Noise in SiGe Channel pMOSFETs on Ultra‐Thin Body SOI with Ni‐Silicided Source/Drain

The low‐frequency noise in buried SiGe channel pMOSFETs fabricated on ultra‐thin body silicon‐on‐insulator (SOI) substrates is investigated. The total thickness of the Si/SiGe/Si body structure, which is fully depleted (FD), is 20 nm. The low‐frequency noise properties are compared with FD SOI pMOSFETs with a 20 nm Si body. The effect of the Ni‐silicide used in the Source/Drain were also studied, especially the case of Schottky‐Barrier (SB) MOSFETs when the Ni‐silicide is formed at the edges of the channel.

Device Integration Issues Towards 10 nm MOSFETs

An overview of critical integration issues for future generation MOSFETs towards 10 nm gate length is presented. Novel materials and innovative structures are discussed. Implementation of high kappa gate dielectrics is presented and device performance is demonstrated for TiN metal gate surface channel SiGe MOSFETs with a gate stack based on ALD-formed HfO2/Al2O3. Low frequency noise properties for those devices are also analyzed. A selective SiGe epitaxy process for low resistivity source/drain contacts has been developed and implemented in pMOSFETs. A spacer pattering technology using optical lithography to fabricate sub 50 nm high-frequency MOSFETs and nanowires is demonstrated. Finally ultra thin body SOI devices with high mobility SiGe channels are demonstrated

Influence of gate width on 50 nm gate length Si/sub 0.7/Ge/sub 0.3/ channel PMOSFETs

Compressively strained Si/sub 0.7/Ge/sub 0.3/ channel PMOSFETs were fabricated and the effective hole mobility was found to be 20-30 % higher in the Si/sub 0.7/Ge/sub 0.3/ devices than in their Si counterparts. The g/sub m/, normalized to gate width, was found to increase strongly with decreasing gate width in the Si/sub 0.7/Ge/sub 0.3/ devices, a behavior that was not found in the Si devices. All the Si/sub 0.7/Ge/sub 0.3/ devices down to 50 nm gate length showed enhanced g/sub m/ compared to the Si devices for gate widths <1 /spl mu/m. At L = 50 nm and W = 0.25 /spl mu/m the Si/sub 0.7/Ge/sub 0.3/ devices exhibited increased g/sub m/ and I/sub D/ of about 15 %, in saturation, compared to the Si devices, I/sub on/ was 286 /spl mu/A//spl mu/m and I/sub off/ was 0.23 nA//spl mu/m at V/sub dd/ = 1.5 V for the Si/sub 0.7/Ge/sub 0.3/ device.

Enhanced Intrinsic Gain (gm/gd) of PMOSFETs with a Si

PMOSFETs with a Si0.7Ge0.3 channel were fabricated. The intrinsic gain of the Si0.7Ge0.3 channel PMOSFET was compared to a reference Si PMOSFET, and was found to be enhanced by about 20 to 30 % for all gate lengths down to 0.3 Pm. This enhancement is attributed to an increased effective mobility in the Si0.7Ge0.3 channel. The inclusion of a Si0.7Ge0.3 channel was found to degrade neither the output conductance (go) nor the breakdown voltage.