Bengt Gunnar Malm

Comprehensive study on low-frequency noise and mobility in Si and SiGe pMOSFETs with high-/spl kappa/ gate dielectrics and TiN gate

Low-frequency noise and hole mobility are studied in Si and SiGe surface channel pMOSFETs with various types of high-/spl kappa/ dielectric stacks (Al/sub 2/O/sub 3/, Al/sub 2/O/sub 3//HfAlO/sub x//Al/sub 2/O/sub 3/ and Al/sub 2/O/sub 3//HfO/sub 2//Al/sub 2/O/sub 3/) and TiN as gate electrode material. Comparisons are made with poly-SiGe-gated pMOSFETs as well as poly-Si/SiO/sub 2//Si references. The choice of channel material (strained SiGe or Si), gate material (TiN or poly-SiGe), and high-/spl kappa/ material (Al/sub 2/O/sub 3/, HfO/sub 2/, HfAlO/sub x/) is discussed in terms of mobility and low-frequency noise. A TiN gate in combination with a surface SiGe channel is advantageous both for enhanced mobility and low 1/f noise. The dominant sources of carrier scattering are identified by analyzing the mobility measured at elevated temperatures. The 1/f noise is studied from subthreshold to strong inversion conditions and at different substrate biases. The mobility fluctuation noise model and the number fluctuation noise model are both used to investigate the 1/f-noise origin.

500

Successful operation of low-voltage 4H-SiC n-p-n bipolar transistors and digital integrated circuits based on emitter coupled logic is reported from -40 °C to 500 °C. Nonmonotonous temperature dependence (previously predicted by simulations but now measured) was observed for the transistor current gain; in the range -40 °C-300 °C it decreased when the temperature increased, while it increased in the range 300 °C-500 °C. Stable noise margins of ~ 1 V were measured for a 2-input OR/NOR gate operated on -15 V supply voltage from 0 °C to 500 °C for both OR and NOR output.

^{\circ}{\rm C}

Accurate physical modeling has been developed to describe the current gain of silicon carbide (SiC) power bipolar junction transistors (BJTs), and the results have been compared with measurements. Interface traps between SiC and SiO2 have been used to model the surface recombination by changing the trap profile, capture cross section, and concentration. The best agreement with measurement is obtained using one single energy level at 1 eV above the valence band, a capture cross section of 1 × 10-5 cm2, and a trap concentration of 2 × 1012 cm-2. Simulations have been performed at different temperatures to validate the model and characterize the temperature behavior of SiC BJTs. An analysis of the carrier concentration at different collector currents has been performed in order to describe the mechanisms of the current gain fall-off at a high collector current both at room temperature and high temperatures. At room temperature, high injection in the base (which has a doping concentration of 3 × 1017 cm-3) and forward biasing of the base-collector junction occur simultaneously, causing an abrupt drop of the current gain. At higher temperatures, high injection in the base is alleviated by the higher ionization degree of the aluminum dopants, and then forward biasing of the base-collector junction is the acting mechanism for the current gain fall-off. Forward biasing of the base-collector junction can also explain the reduction of the knee current with increasing temperature by means of the negative temperature dependence of the mobility.

Bipolar Integrated OR/NOR Gate in 4H-SiC

Lateral growth of Ni silicide towards the channel region of metal-oxide-semiconductor transistors (MOSFETs) fabricated on ultrathin silicon-on-insulator (SOI) is characterized using SOI wafers with a 20-nm-thick surface Si layer. With a 10-nm-thick Ni film for silicide formation, p-channel MOSFETs displaying ordinary device characteristics with silicided p+ source/drain regions were demonstrated. No lateral growth of NiSix under gate isolation spacers was found according to electron microscopy. When the Ni film was 20 nm thick, Schottky contact source/drain MOSFETs showing typical ambipolar characteristics were obtained. A severe lateral encroachment of NiSix into the channel region leading to an increased gate leakage was revealed, while no detectable voiding at the silicide front towards the Si channel was observed.

Modeling and Characterization of Current Gain Versus Temperature in 4H-SiC Power BJTs

Operation up to 300 ^°C of low-voltage 4H-SiC n-p-n bipolar transistors and digital integrated circuits based on emitter-coupled logic is demonstrated. Stable noise margins of about 1 V are reported for a two-input or- nor gate operated on - 15 V supply voltage from 27 ^°C up to 300 ^°C. In the same temperature range, an oscillation frequency of about 2 MHz is also reported for a three-stage ring oscillator.

Lateral encroachment of Ni-silicides in the source/drain regions on ultrathin silicon-on-insulator

Strained layer Si/sub 0.7/Ge/sub 0.3/ pMOSFETs were fabricated and shown to exhibit enhanced hole mobility, up to 35% higher for a SiGe device with 3-nm-thick Si-cap, and lower 1/f noise compared to Si surface channel pMOSFETs. The 1/f noise in the investigated devices was dominated by mobility fluctuation noise and found to be lower in the SiGe devices. The source of the mobility fluctuations was determined by investigating the electric field dependence of the 1/f noise. It was found that the SiO/sub 2//Si interface roughness scattering plays an important role for the mobility fluctuation noise, although not dominating the effective mobility. The physical separation of the carriers from the SiO/sub 2//Si interface in the buried SiGe channel pMOSFETs resulted in lower SiO/sub 2//Si interface roughness scattering, which explains the reduction of 1/f noise in these devices. The 1/f noise mechanism was experimentally verified by studying 1/f noise in SiGe devices with various thicknesses of the Si-cap. A too large Si-cap thickness led to a deteriorated carrier confinement in the SiGe channel resulting in that considerable 1/f noise was generated in the parasitic current in the Si-cap. In our experiments, the SiGe devices with a Si-cap thickness in the middle of the interval 3-7 nm exhibited the lowest 1/f noise.

Design and Characterization of High-Temperature ECL-Based Bipolar Integrated Circuits in 4H-SiC

A monolithic bipolar operational amplifier (opamp) fabricated in 4H-SiC technology is presented. The opamp has been used in an inverting negative feedback amplifier configuration. Wide temperature operation of the amplifier is demonstrated from 25°C to 500°C. The measured closed loop gain is around 40 dB for all temperatures whereas the 3 dB bandwidth increases from 270 kHz at 25°C to 410 kHz at 500°C. The opamp achieves 1.46 V/μs slew rate and 0.25% total harmonic distortion. This is the first report on high temperature operation of a fully integrated SiC bipolar opamp which demonstrates the feasibility of this technology for high temperature analog integrated circuits.

1/f noise in Si and Si/sub 0.7/Ge/sub 0.3/ pMOSFETs

Self-heating in a 0.25 /spl mu/m BiCMOS technology with different isolation structures, including shallow and deep trenches on bulk and silicon-on-insulator (SOI) substrates, is characterized experimentally. Thermal resistance values for single- and multifinger emitter devices are extracted and compared to results obtained from two-dimensional, fully coupled electrothermal simulations. The difference in thermal resistance between the investigated isolation structures becomes more important for transistors with a small aspect ratio, i.e., short emitter length. The influence of thermal boundary conditions, including the substrate thermal resistance, the thermal resistance of the first metallization/via layer, and the simulation structure width is investigated. In the device with full dielectric isolation-deep polysilicon-filled trenches on an SOI substrate-accurate modeling of the heat flow in the metallization is found to be crucial. Furthermore, the simulated structure must be made wide enough to account for the large heat flow in the lateral direction.

A Monolithic, 500 °C Operational Amplifier in 4H-SiC Bipolar Technology

Abstract Optimization of implanted collector doping profiles for a high-speed, low-voltage SiGe HBT process has been investigated experimentally and by device simulations. A low-energy antimony implantation has been combined with a standard selectively implanted collector using phosphorous, to achieve improved control of the collector doping profile. The simulations indicate that the narrow n-type doping peak formed by the antimony implantation allows the cut-off frequency f T to be increased without degrading the collector emitter breakdown voltage BV CEO . The fabricated devices demonstrate a highest f T of 60 GHz. Depending on the collector profile BV CEO values between 1.5 and 2 V were obtained.

Self-heating effects in a BiCMOS on SOI technology for RFIC applications

Performance of 4H-SiC BJTs fabricated on a single 100mm wafer with different SiC etching and sacrificial oxidation procedures is compared in terms of peak current gain in relation to base intrinsic sheet resistance. The best performance was achieved when device mesas were defined by inductively coupled plasma etching and a dry sacrificial oxide was grown at 1100 °C.